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FPGAKey Technical Documents
Download DatasheetDESCRIPTION:
The ispGAL22V10, at 7.5ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the industry's first in-system programmable 22V10 device. E2 technology offers high speed (<100ms) erase times, providing the ability to reprogram or reconfigure the device quickly and efficiently.The generic architecture provides maximum design flexibility by allowing the Output Logic Macrocell (OLMC) to be configured by the user. The ispGAL22V10 is fully function/fuse map/parametric compatible with standard bipolar and CMOS 22V10 devices. The standard PLCC package provides the same functional pinout as the standard 22V10 PLCC package with No-Connect pins being used for the ISP interface signals. Unique test circuitry and reprogrammable cells allow complete AC, DC, and functional testing during manufacture. As a result, Lattice Semiconductor delivers 100% field programmability and functionality of all GAL products. In addition, 10,000 erase/write cycles and data retention in excess of 20 years are specified.
FEATURE:
·IN-SYSTEM PROGRAMMABLETM(5-V ONLY)-4-Wire Serial Programming Interface-Minimum 10,000 Program/Erase Cycles
- Built-in Pull-Down on SDI Pin Eliminates Discrete Resistor on Board(ispGAL22V10C Only)·HIGH PERFORMANCE ERCMOS?TECHNOLOGY
- 7.5ns Maximum Propagation Delay一Fmax=111 MHz一5ns Maximum from Clock Input to Data Output一UltraMOS?Advanced CMOS Technology
· ACTIVE PULL-UPS ON ALL LOGIC INPUT AND I/O PINS
· COMPATIBLE WITH STANDARD 22V10 DEVICES
— Fully Function/Fuse-Map/Parametric Compatible with Bipolar and CMOS 22V10 Devices
· E2 CELL TECHNOLOGY
- In-System Programmable Logic一100%Tested/100%Yields
- High Speed Electrical Erasure(<100ms)
一 20Year Data Retention
· TEN OUTPUT LOGIC MACROCELLS
- Maximum Flexibility for Complex Logic Designs
· APPLICATIONS INCLUDE:
- DMA Control一State Machine Control
- High Speed Graphics Processing
- Software-Driven Hardware Configuration
· ELECTRONIC SIGNATURE FOR IDENTIFICATION
■ High Performance
• tPD = 2.3ns propagation delay
• fMAX = 455 MHz maximum operating frequency
• tCO = 2ns maximum from clock input to data output
• tSU = 1.3 ns clock set-up time
■ Low Power
• 1.8V core E2 CMOS technology
• Typical standby power <300µW (ispGAL22V10AC)
• CMOS design techniques provide low static and dynamic power
■ Space-Saving Packaging
• Available in 32-pin QFNS (Quad Flat-pack, No lead, Saw-singulated) package 5mm x 5mm body size1
■ Easy System Integration
• Operation with 3.3V (ispGAL22V10AV), 2.5V
(ispGAL22V10AB) or 1.8V (ispGAL22V10AC)supplies
• Operation with 3.3V, 2.5V or 1.8V LVCMOS I/O
• 5V tolerant I/O for LVCMOS 3.3 interface
• Hot-socketing
• Open-drain capability
• Input pull-up, pull-down or bus-keeper
• Lead-free package option
• Programmable output slew rate
• 3.3V PCI compatible
■ In-System Programmable
• IEEE 1149.1 boundary scan testable
• 3.3V/2.5V/1.8V in-system programmable
(ISP) using IEEE 1532 compliant interface
■ E2 CELL TECHNOLOGY
• In-system programmable logic
• 100% tested/100% yields
• High speed electrical erasure (<50ms)
• DMA control
• State machine control
• High speed graphics processing
• Software-driven hardware configuration
Artificial Intelligence
5G Technology
Cloud Computing
Consumer Electronics
Wireless Technology
Industrial Control
Internet of Things
Medical Equipment
| Specification | Value |
|---|---|
| Logic Family | ispGAL |
| Number of Macrocells | 10 |
| Maximum Operating Frequency | 111 MHz |
| Delay Time | 7.5 ns |
| Operating Supply Voltage | 4.75 V to 5.25 V |
| Supply Current | 140 mA |
| Maximum Operating Temperature | + 75 C |
| Minimum Operating Temperature | 0 C |
| Mounting Style | SMD/SMT |
| Package / Case | PLCC-28 |
| Operating Temperature | 0 C to + 75 C |
| Packaging | Tube |
| Factory Pack Quantity | 37 |
| Supply Voltage - Max | 5.25 V |
| Supply Voltage - Min | 4.75 V |
2+ $21.3462
25+ $13.5206
100+ $10.1438
500+ $8.1204
1000+ $7.2494
2+ $19.2692
25+ $17.0046
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