ICE40LP384-SG32TR of Lattice iCE40 LP/HX Family

ICE40LP384-SG32TR FPGAs Overview

The iCE40 family of ultra-low power, non-volatile FPGAs has five devices with densities ranging from 384 to 7680 Look-Up Tables (LUTs). In addition to LUT-based, low-cost programmable logic, these devices feature Embedded Block RAM (EBR), Non-volatile Configuration Memory (NVCM) and Phase Locked Loops (PLLs). These features allow the devices to be used in low-cost, high-volume consumer and system applications. Select packages offer High-Current drivers that are ideal to drive three white LEDs, or one RGB LED. The iCE40 devices are fabricated on a 40 nm CMOS low power process. The device architecture has several features such as programmable low-swing differential I/Os and the ability to turn off on-chip PLLs dynamically. These features help manage static and dynamic power consumption, resulting in low static power for all members of the family. The iCE40 devices are available in two versions – ultra low power (LP) and high performance (HX) devices.

The iCE40 FPGAs are available in a broad range of advanced halogen-free packages ranging from the space saving 1.40x1.48 mm WLCSP to the PCB-friendly 20x20 mm TQFP. Table 1-1 shows the LUT densities, package and I/O options, along with other key parameters. The iCE40 devices offer enhanced I/O features such as pull-up resistors. Pull-up features are controllable on a

“per-pin” basis. The iCE40 devices also provide flexible, reliable and secure configuration from on-chip NVCM. These devices can also configure themselves from external SPI Flash or be configured by an external master such as a CPU.

Lattice provides a variety of design tools that allow complex designs to be efficiently implemented using the iCE40 family of devices. Popular logic synthesis tools provide synthesis library support for iCE40. Lattice design tools use the synthesis tool output along with the user-specified preferences and constraints to place and route the design in the iCE40 device. These tools extract the timing from the routing and back-annotate it into the design for timing verification.

The Lattice FPGA series ICE40LP384-SG32TR is FPGA iCE40 LP Family 384 Cells 40nm Technology 1.2V 32-Pin QFN EP T/R, View Substitutes & Alternatives along with datasheets, stock, pricing from Authorized Distributors at FPGAkey.com, and you can also search for other FPGAs products.

Features

 Flexible Logic Architecture

• Five devices with 384 to 7,680 LUT4s and 10 to 206 I/Os

 Ultra Low Power Devices

• Advanced 40 nm low power process

• As low as 21 µA standby power

• Programmable low swing differential I/Os

 Embedded and Distributed Memory

• Up to 128 kbits sysMEM Embedded Block RAM

 Pre-Engineered Source Synchronous I/O

• DDR registers in I/O cells

 High Current LED Drivers

• Three High Current Drivers used for three different LEDs or one RGB LED

 High Performance, Flexible I/O Buffer

• Programmable sysIO buffer supports wide range of interfaces:

— LVCMOS 3.3/2.5/1.8

— LVDS25E, subLVDS

— Schmitt trigger inputs, to 200 mV typical hysteresis

• Programmable pull-up mode

 Flexible On-Chip Clocking

• Eight low-skew global clock resources

• Up to two analog PLLs per device

 Flexible Device Configuration

• SRAM is configured through:

— Standard SPI Interface

— Internal Nonvolatile Configuration Memory (NVCM)

 Broad Range of Package Options

• WLCSP, QFN, VQFP, TQFP, ucBGA, caBGA, and csBGA package options

• Small footprint package options

— As small as 1.40 mm x 1.48 mm

• Advanced halogen-free packaging

FAQ

Q: Does the price of ICE40LP384-SG32TR devices fluctuate frequently?
The FPGAkey search engine monitors the ICE40LP384-SG32TR inventory quantity and price of global electronic component suppliers in real time, and regularly records historical price data. You can view the historical price trends of electronic components to provide a basis for your purchasing decisions.
Q: Do I have to sign up on the website to make an inquiry for ICE40LP384-SG32TR?
No, only submit the quantity, email address and other contact information required for the inquiry of ICE40LP384-SG32TR, but you need to sign up for the post comments and resource downloads.
Q: How can I obtain software development tools related to the Lattice FPGA platform?
Lattice's development environment uses Diamone. These recommendations are all reference opinions. The specific choice depends on personal habits and functional requirements to specifically select a more suitable match. You can search and download through the FPGA resource channel.
Q: Where can I purchase Lattice iCE40LP384 Development Boards, Evaluation Boards, or iCE40 LP/HX Starter Kit? also provide technical information?
FPGAkey does not provide development board purchase services for the time being, but customers often consult about ZedBoard, Basys 3 board, TinyFPGA BX, Nexys4-DDR, Terasic DE10-Nano, Digilent Arty S7, etc. If you need relevant technical information, you can submit feedback information, our technicians will contact you soon.
Q: How to obtain ICE40LP384-SG32TR technical support documents?
Enter the "ICE40LP384-SG32TR" keyword in the search box of the website, or find these through the Download Channel or FPGA Forum .
Q: What should I do if I did not receive the technical support for ICE40LP384SG32TR in time?
Depending on the time difference between your location and our location, it may take several hours for us to reply, please be patient, our FPGA technical engineer will help you with the ICE40LP384-SG32TR pinout information, replacement, datasheet in pdf, programming tools, starter kit, etc.

Application Field

Artificial Intelligence
5G Technology
Cloud Computing
Consumer Electronics
Wireless Technology
Industrial Control
Internet of Things
Medical Equipment

ICE40LP384-SG32TR Specifications

Specification	Value
Number of LABs/CLBs	48
Number of Logic Elements/Cells	384
Number of I/O	21
Voltage - Supply	1.14V ~ 1.26V
Mounting Type	Surface Mount
Operating Temperature	-40℃ ~ 100℃ (TJ)
Package / Case	32-VFQFN Exposed Pad
Supplier Device Package	32-QFN (5x5)