$0 - $55.147 | 1 Pieces(Min. Order)
Lattice
PDIP-24
No RoHS
Obsolete
Factory Excess Stock / Franchised Distributor
SPLD - Simple Programmable Logic Devices
SPLD GAL Family 10 Macro Cells 5V 24-Pin PDIP
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FPGAKey Technical Documents
Download DatasheetThe GAL22V10, at 4ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2 ) floating gate technology to provide the highest performance available of any 22V10 device on the market. CMOS circuitry allows the GAL22V10D-15LP to consume much less power when compared to bipolar 22V10 devices. E2 technology offers high speed (<100ms) erase times, providing the ability to reprogram or reconfigure the device quickly and efficiently.
The generic architecture provides maximum design flexibility by allowing the Output Logic Macrocell (OLMC) to be configured by the user. The GAL22V10D-15LP is fully function/fuse map/parametric compatible with standard bipolar and CMOS 22V10 devices.
Unique test circuitry and reprogrammable cells allow complete AC, DC, and functional testing during manufacture. As a result, Lattice Semiconductor delivers 100% field programmability and functionality of all GAL products. In addition, 100 erase/write cycles and data retention in excess of 20 years are specified.
The Lattice SPLD - Simple Programmable Logic Devices series GAL22V10D-15LP is SPLD GAL Family 10 Macro Cells 5V 24-Pin PDIP, View Substitutes & Alternatives along with datasheets, stock, pricing from Authorized Distributors at FPGAkey.com, and you can also search for other FPGAs products.• HIGH PERFORMANCE E2CMOS TECHNOLOGY
— 4 ns Maximum Propagation Delay
— Fmax = 250 MHz
— 3.5 ns Maximum from Clock Input to Data Output
— UltraMOS Advanced CMOS Technology
• ACTIVE PULL-UPS ON ALL PINS
• COMPATIBLE WITH STANDARD 22V10 DEVICES
— Fully Function/Fuse-Map/Parametric Compatible with Bipolar and UVCMOS 22V10 Devices
• 50% to 75% REDUCTION IN POWER VERSUS BIPOLAR
— 90mA Typical Icc on Low Power Device
— 45mA Typical Icc on Quarter Power Device
• E2 CELL TECHNOLOGY
— Reconfigurable Logic
— Reprogrammable Cells
— 100% Tested/100% Yields
— High Speed Electrical Erasure (<100ms)
— 20 Year Data Retention
• TEN OUTPUT LOGIC MACROCELLS
— Maximum Flexibility for Complex Logic Designs
• PRELOAD AND POWER-ON RESET OF REGISTERS
— 100% Functional Testability
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Logic Family
GAL
Number of Macrocells
10
Maximum Operating Frequency
83.3 MHz
Delay Time
15 ns
Operating Supply Voltage
4.75 V to 5.25 V
Supply Current
90 mA
Maximum Operating Temperature
+ 75 C
Minimum Operating Temperature
0 C
Mounting Style
Through Hole
Package / Case
PDIP-24
Operating Temperature
0 C to + 75 C
Packaging
Tube
Factory Pack Quantity
300
Supply Voltage - Max
5.25 V
Supply Voltage - Min
4.75 V
1+ $4.48
1+ $3.95
1+ $4.93
1+ 0
1+ 0
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