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Download DatasheetDescription
The GAL20XV10B-15LP combines a high performance CMOS process with electrically erasable (E2) floating gate technology to provide the highest speed Exclusive-OR PLD available in the market. At 90mA maximum Icc (75mA typical Icc), the GAL20XV10B-15LP provides a substantial savings in power when compared to bipolar counterparts. E2CMOS technology offers high speed (<100ms) erase times providing the ability to reprogram, reconfigure or test the devices quickly and efficiently. The generic architecture provides maximum design flexibility by allowing the Output Logic Macrocell (OLMC) to be configured by the user. An important subset of the many architecture configurations possible with the GAL20XV10B-15LP are the PAL® architectures listed in the macrocell description section of this document. The GAL20XV10B-15LP is capable of emulating these PAL architectures with full function and parametric compatibility. Unique test circuitry and reprogrammable cells allow complete AC, DC, and functional testing during manufacturing. As a result, Lattice Semiconductor delivers 100% field programmability and functionality of all GAL products. In addition, 100 erase/write cycles and data retention in excess of 20 years are specified.
Features
• HIGH PERFORMANCE E2CMOS ® TECHNOLOGY
— 10 ns Maximum Propagation Delay
— Fmax = 100 MHz
— 7 ns Maximum from Clock Input to Data Output
— TTL Compatible 16 mA Outputs
— UltraMOS® Advanced CMOS Technology
• 50% to 75% REDUCTION IN POWER FROM BIPOLAR
— 90mA Maximum Icc
— 75mA Typical Icc
• ACTIVE PULL-UPS ON ALL PINS
• E2 CELL TECHNOLOGY
— Reconfigurable Logic
— Reprogrammable Cells
— 100% Tested/100% Yields
— High Speed Electrical Erasure (<100 ms)
— 20 Year Data Retention
• TEN OUTPUT LOGIC MACROCELLS
— XOR Gate Capability on all Outputs
— Full Function and Parametric Compatibility with PAL12L10, 20L10, 20X10, 20X8, 20X4
— Registered or Combinatorial with Polarity
• PRELOAD AND POWER-ON RESET OF ALL REGISTERS
The Lattice SPLD - Simple Programmable Logic Devices series GAL20XV10B-15LP is High-Speed E2CMOS PLD Generic Array Logic™, View Substitutes & Alternatives along with datasheets, stock, pricing from Authorized Distributors at FPGAkey.com, and you can also search for other FPGAs products.• HIGH PERFORMANCE E2CMOS TECHNOLOGY
— 10 ns Maximum Propagation Delay
— Fmax = 100 MHz
— 7 ns Maximum from Clock Input to Data Output
— TTL Compatible 16 mA Outputs
— UltraMOS Advanced CMOS Technology
• 50% to 75% REDUCTION IN POWER FROM BIPOLAR
— 90mA Maximum Icc
— 75mA Typical Icc
• ACTIVE PULL-UPS ON ALL PINS
• E2 CELL TECHNOLOGY
— Reconfigurable Logic
— Reprogrammable Cells
— 100% Tested/100% Yields
— High Speed Electrical Erasure (<100 ms)
— 20 Year Data Retention
• TEN OUTPUT LOGIC MACROCELLS
— XOR Gate Capability on all Outputs
— Full Function and Parametric Compatibility with PAL12L10, 20L10, 20X10, 20X8, 20X4
— Registered or Combinatorial with Polarity
• PRELOAD AND POWER-ON RESET OF ALL REGISTERS
— High Speed Counters
— Graphics Processing
— Comparators
Artificial Intelligence
5G Technology
Cloud Computing
Consumer Electronics
Wireless Technology
Industrial Control
Internet of Things
Medical Equipment
Specification | Value |
---|---|
Logic Family | GAL |
Number of Macrocells | 10 |
Maximum Operating Frequency | 83.3 MHz |
Delay Time | 15 ns |
Operating Supply Voltage | 4.75 V to 5.25 V |
Supply Current | 90 mA |
Maximum Operating Temperature | + 75 C |
Minimum Operating Temperature | 0 C |
Mounting Style | Through Hole |
Package / Case | PDIP-24 |
Number of Product Terms per Macro | 4 |
Operating Temperature | 0 C to + 75 C |
Factory Pack Quantity | 300 |
Supply Voltage - Max | 5.25 V |
Supply Voltage - Min | 4.75 V |
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