GAL20XV10B-10LJ of Lattice SPLD GAL Family

GAL20XV10B-10LJ FPGAs Overview

The GAL20XV10B-10LJ combines a high performance CMOS process with electrically erasable (E2) floating gate technology to provide the highest speed Exclusive-OR PLD available in the market. At 90mA maximum Icc (75mA typical Icc), the GAL20XV10B-10LJ provides a substantial savings in power when compared to bipolar counterparts. E2CMOS technology offers high speed (<100ms) erase times providing the ability to reprogram, reconfigure or test the devices quickly and efficiently.

The generic architecture provides maximum design flexibility by allowing the Output Logic Macrocell (OLMC) to be configured by the user. An important subset of the many architecture configurations possible with the GAL20XV10B-10LJ are the PAL architectures listed in the macrocell description section of this document. The GAL20XV10B-10LJ is capable of emulating these PAL architectures with full function and parametric compatibility.

Unique test circuitry and reprogrammable cells allow complete AC, DC, and functional testing during manufacturing. As a result, Lattice Semiconductor delivers 100% field programmability and functionality of all GAL products. In addition, 100 erase/write cycles and data retention in excess of 20 years are specified.

The Lattice SPLD - Simple Programmable Logic Devices series GAL20XV10B-10LJ is High-Speed E2CMOS PLD Generic Array Logic,SPLD - Simple Programmable Logic Devices Use GAL20V8B/C, View Substitutes & Alternatives along with datasheets, stock, pricing from Authorized Distributors at FPGAkey.com, and you can also search for other FPGAs products.

Features

• HIGH PERFORMANCE E2CMOS TECHNOLOGY

— 10 ns Maximum Propagation Delay

— Fmax = 100 MHz

— 7 ns Maximum from Clock Input to Data Output

— TTL Compatible 16 mA Outputs

— UltraMOS Advanced CMOS Technology

• 50% to 75% REDUCTION IN POWER FROM BIPOLAR

— 90mA Maximum Icc

— 75mA Typical Icc

• ACTIVE PULL-UPS ON ALL PINS

• E2 CELL TECHNOLOGY

— Reconfigurable Logic

— Reprogrammable Cells

— 100% Tested/100% Yields

— High Speed Electrical Erasure (<100 ms)

— 20 Year Data Retention

• TEN OUTPUT LOGIC MACROCELLS

— XOR Gate Capability on all Outputs

— Full Function and Parametric Compatibility with PAL12L10, 20L10, 20X10, 20X8, 20X4

— Registered or Combinatorial with Polarity

• PRELOAD AND POWER-ON RESET OF ALL REGISTERS

Applications

— High Speed Counters

— Graphics Processing

— Comparators

FAQ

Q: Does the price of GAL20XV10B-10LJ devices fluctuate frequently?
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Q: How can I obtain software development tools related to the Lattice FPGA platform?
Lattice's development environment uses Diamone. These recommendations are all reference opinions. The specific choice depends on personal habits and functional requirements to specifically select a more suitable match. You can search and download through the FPGA resource channel.
Q: Where can I purchase Lattice GAL20XV10 Development Boards, Evaluation Boards, or SPLD GAL Starter Kit? also provide technical information?
FPGAkey does not provide development board purchase services for the time being, but customers often consult about ZedBoard, Basys 3 board, TinyFPGA BX, Nexys4-DDR, Terasic DE10-Nano, Digilent Arty S7, etc. If you need relevant technical information, you can submit feedback information, our technicians will contact you soon.
Q: How to obtain GAL20XV10B-10LJ technical support documents?
Enter the "GAL20XV10B-10LJ" keyword in the search box of the website, or find these through the Download Channel or FPGA Forum .
Q: What should I do if I did not receive the technical support for GAL20XV10B10LJ in time?
Depending on the time difference between your location and our location, it may take several hours for us to reply, please be patient, our FPGA technical engineer will help you with the GAL20XV10B-10LJ pinout information, replacement, datasheet in pdf, programming tools, starter kit, etc.

Application Field

Artificial Intelligence
5G Technology
Cloud Computing
Consumer Electronics
Wireless Technology
Industrial Control
Internet of Things
Medical Equipment

GAL20XV10B-10LJ Specifications

Specification	Value
Logic Family	GAL
Number of Macrocells	10
Maximum Operating Frequency	100 MHz
Delay Time	10 ns
Operating Supply Voltage	4.75 V to 5.25 V
Supply Current	90 mA
Maximum Operating Temperature	+ 75 C
Minimum Operating Temperature	0 C
Mounting Style	SMD/SMT
Package / Case	PLCC-28
Number of Product Terms per Macro	4
Operating Temperature	0 C to + 75 C
Packaging	Tube / Tray
Factory Pack Quantity	37
Supply Voltage - Max	5.25 V
Supply Voltage - Min	4.75 V