GAL18V10B-20LP FPGAs Overview
The GAL18V10, at 7.5 ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2
) floating gate technology to provide a very flexible 20-pin
PLD. CMOS circuitry allows the GAL18V10B-20LP to consume much less
power when compared to its bipolar counterparts. The E2
technology offers high speed (<100ms) erase times, providing the ability
to reprogram or reconfigure the device quickly and efficiently.
By building on the popular 22V10 architecture, the GAL18V10
eliminates the learning curve usually associated with using a new
device architecture. The generic architecture provides maximum
design flexibility by allowing the Output Logic Macrocell (OLMC)
to be configured by the user. The GAL18V10B-20LP OLMC is fully compatible with the OLMC in standard bipolar and CMOS 22V10 devices.
Unique test circuitry and reprogrammable cells allow complete AC,
DC, and functional testing during manufacture. As a result, Lattice
Semiconductor delivers 100% field programmability and functionality of all GAL products. In addition, 100 erase/write cycles and
data retention in excess of 20 years are specified.
The Lattice SPLD - Simple Programmable Logic Devices series GAL18V10B-20LP is High Performance E2CMOS PLD Generic Array Logic,SPLD - Simple Programmable Logic Devices 18 Input 10 Output 5V Low Power 20ns, View Substitutes & Alternatives along with datasheets, stock, pricing from Authorized Distributors at FPGAkey.com,
and you can also search for other FPGAs products.
• HIGH PERFORMANCE E2CMOS TECHNOLOGY
— 7.5 ns Maximum Propagation Delay
— Fmax = 111 MHz
— 5.5 ns Maximum from Clock Input to Data Output
— TTL Compatible 16 mA Outputs
— UltraMOS Advanced CMOS Technology
• LOW POWER CMOS
— 75 mA Typical Icc
• ACTIVE PULL-UPS ON ALL PINS
— Reconfigurable Logic
— Reprogrammable Cells
— 100% Tested/100% Yields
— High Speed Electrical Erasure (<100ms)
— 20 Year Data Retention
• TEN OUTPUT LOGIC MACROCELLS
— Uses Standard 22V10 Macrocell Architecture
— Maximum Flexibility for Complex Logic Designs
• PRELOAD AND POWER-ON RESET OF REGISTERS
— 100% Functional Testability
• APPLICATIONS INCLUDE:
— DMA Control
— State Machine Control
— High Speed Graphics Processing
— Standard Logic Speed Upgrade
• ELECTRONIC SIGNATURE FOR IDENTIFICATION
Q: Does the price of GAL18V10B-20LP devices fluctuate frequently?
The FPGAkey search engine monitors the GAL18V10B-20LP inventory quantity and price of global electronic component suppliers in real time,
and regularly records historical price data. You can view the historical price trends of electronic components to provide a basis for your
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No, only submit the quantity, email address and other contact information required for the inquiry of GAL18V10B-20LP, but you need to
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Q: How can I obtain software development tools related to the Lattice FPGA platform?
Lattice's development environment uses Diamone. These recommendations are all reference opinions.
The specific choice depends on personal habits and functional requirements to specifically select a more suitable match.
You can search and download through the FPGA resource channel.
Q: Where can I purchase Lattice GAL18V10 Development Boards, Evaluation Boards,
or SPLD GAL Starter Kit? also provide technical information?
FPGAkey does not provide development board purchase services for the time being, but customers often consult about ZedBoard, Basys 3 board,
TinyFPGA BX, Nexys4-DDR, Terasic DE10-Nano, Digilent Arty S7, etc. If you need relevant technical information,
you can submit feedback information, our technicians will contact you soon.
Q: How to obtain GAL18V10B-20LP technical support documents?
Enter the "GAL18V10B-20LP" keyword in the search box of the website, or find these through the Download Channel or FPGA Forum .
Q: What should I do if I did not receive the technical support for GAL18V10B20LP in time?
Depending on the time difference between your location and our location, it may take several hours for us to reply, please be patient, our FPGA technical engineer will help you with the GAL18V10B-20LP pinout information, replacement, datasheet in pdf, programming tools, starter kit, etc.
Internet of Things
Number of Macrocells
Maximum Operating Frequency
Operating Supply Voltage
4.75 V to 5.25 V
Maximum Operating Temperature
+ 75 C
Minimum Operating Temperature
Package / Case
0 C to + 75 C
Factory Pack Quantity
Supply Voltage - Max
Supply Voltage - Min
GAL18V10 Specifications SPLD GAL Family Data sheet