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Download DatasheetThe GAL16LV8D, at 3.5 ns maximum propagation delay time, provides the highest speed performance available in the PLD market. The GAL16LV8C can interface with both 3.3V and 5V signal levels. The GAL16LV8C-10LJ is manufactured using Lattice Semiconductor's advanced 3.3V E2 CMOS process, which combines CMOS with Electrically Erasable (E2 ) floating gate technology. High speed erase times (<100ms) allow the devices to be reprogrammed quickly and efficiently.
The 3.3V GAL16LV8C-10LJ uses the same industry standard 16V8 architecture as its 5V counterpart and supports all architectural features such as combinatorial or registered macrocell operations.
Unique test circuitry and reprogrammable cells allow complete AC, DC, and functional testing during manufacture. As a result, Lattice Semiconductor delivers 100% field programmability and functionality of all GAL products. In addition, 100 erase/write cycles and data retention in excess of 20 years are specified.
The Lattice SPLD - Simple Programmable Logic Devices series GAL16LV8C-10LJ is Aluminum Snap-In Capacitor; Capacitance: 680uF; Voltage: 250V; Case Size: 30x25 mm; Packaging: Bulk,SPLD - Simple Programmable Logic Devices LO VOLT E2CMOS PLD, View Substitutes & Alternatives along with datasheets, stock, pricing from Authorized Distributors at FPGAkey.com, and you can also search for other FPGAs products.• HIGH PERFORMANCE E2CMOS TECHNOLOGY
— 3.5 ns Maximum Propagation Delay
— Fmax = 250 MHz
— 2.5 ns Maximum from Clock Input to Data Output
— UltraMOS Advanced CMOS Technology
• 3.3V LOW VOLTAGE 16V8 ARCHITECTURE
— JEDEC-Compatible 3.3V Interface Standard
— 5V Compatible Inputs
— I/O Interfaces with Standard 5V TTL Devices (GAL16LV8C)
• ACTIVE PULL-UPS ON ALL PINS (GAL16LV8D Only)
• E2 CELL TECHNOLOGY
— Reconfigurable Logic
— Reprogrammable Cells
— 100% Tested/100% Yields
— High Speed Electrical Erasure (<100ms)
— 20 Year Data Retention
• EIGHT OUTPUT LOGIC MACROCELLS
— Maximum Flexibility for Complex Logic Designs
— Programmable Output Polarity
• PRELOAD AND POWER-ON RESET OF ALL REGISTERS
— 100% Functional Testability
— Glue Logic for 3.3V Systems
— DMA Control
— State Machine Control
— High Speed Graphics Processing
— Standard Logic Speed Upgrade
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| Specification | Value |
|---|---|
| Logic Family | GAL |
| Number of Macrocells | 8 |
| Maximum Operating Frequency | 83.3 MHz |
| Delay Time | 10 ns |
| Operating Supply Voltage | 3 V to 3.6 V |
| Supply Current | 65 mA |
| Maximum Operating Temperature | + 75 C |
| Minimum Operating Temperature | 0 C |
| Mounting Style | SMD/SMT |
| Package / Case | PLCC-20 |
| Number of Product Terms per Macro | 8 |
| Operating Temperature | 0 C to + 75 C |
| Packaging | Tube |
| Factory Pack Quantity | 460 |
| Supply Voltage - Max | 3.6 V |
| Supply Voltage - Min | 3 V |
1+ $5.4100
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