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Lattice SuperWIDE High Density PLD

SuperWIDE High Density PLD

ARCHITECTURE FEATURES  
— Enhanced Pin-Locking Architecture with SingleLevel Global Routing Pool and SuperWIDE GLBs
— Wrap Around Product Term Sharing Array Supports up to 35 Product Terms Per Macrocell
— Macrocells Support Concurrent Combinatorial and Registered Functions
— Macrocell Registers Feature Multiple Control Options Including Set, Reset and Clock Enable
— Four Dedicated Clock Input Pins Plus Macrocell Product Term Clocks
— Programmable I/O Supports Programmable Bus Hold, Pull-up, Open Drain and Slew Rate Options
— Four Global Product Term Output Enables, Two Global OE Pins and One Product Term OE per Macrocell

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