• SuperBIG HIGH DENSITY IN-SYSTEM
PROGRAMMABLE LOGIC
— Enhanced Pin-Locking Architecture, Symmetrical Generic Logic Blocks Connected by Hierarchical Big Fast Megablock and Global Routing Planes
— Product Term Sharing Array Supports up to 28 Product Terms per Macrocell Output
— Macrocells Support Concurrent Combinatorial and Registered Functions
— Embedded Tristate Bus Can Be Used as an Internal Tristate Bus or as an Extension of an External Tristate Bus
— Macrocell and I/O Registers Feature Multiple Control Options, Including Set, Reset and Clock Enable
— I/O Pins Support Programmable Bus Hold, Pull-Up, Open-Drain and Slew Rate Options
— Separate VCCIO Power Supply to Support 3.3V or 2.5V Input/Output Logic Levels
— I/O Cell Register Programmable as Input Register for Fast Setup Time or Output Register for Fast Clock toOutput Time
Support
