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Lattice PALCE610 Family

PALCE610 Family

The PALCE610 is a general purpose PAL device and is functionally and fuse map equivalent to the EP610. It can accommodate logic functions with up to 20 inputs and 16 outputs. There are 16 I/O macrocells that can be individually configured to the user’s specifications. The macrocells can be configured as either registered or combinatorial. The registers can be configured as D, T, J-K, or S-R flip-flops. The PALCE610 uses the familiar sum-of-products logic with programmable-AND and fixed-OR structure. Eight product terms are brought to each macrocell to provide logic implementations. The PALCE610 is manufactured using advanced CMOS EE technology providing low power consumption. Moreover, it is a high-speed device having a worstcase tPD of 15 ns. Space-saving 24-pin SKINNYDIP and 28-pin PLCC packages are offered. This device can be quickly erased and reprogrammed providing for easy prototyping. Once a device is programmed the security bit can be used to provide protection from copying a proprietary design.


The PALCE610 is a general purpose programmable logic device. It has 16 independently-configurable macrocells. Each macrocell can be configured as either combinatorial or registered. The registers can be D, T, J-K, or S-R type flip-flops. The device has 4 dedicated input pins and 2 clock pins. Each clock pin controls 8 of the 16 macrocells. The programming matrix implements a programmable AND logic array which drives a fixed OR logic array. Buffers for device inputs have complementary outputs to provide user-programmable input polarity. Unused input pins should be tied to VCC or ground. The array uses our electrically erasable technology. An unprogrammed bit is disconnected and a programmed bit is connected. Product terms with all bits unprogrammed assume the logical-HIGH state and product terms with both the TRUE and Complement bits programmed assume the logical-LOW state. The programmable functions in the PALCE610 are automatically configured from the user’s design specifications, which can be in a number of formats. The design specification is processed by development software to verify the design and create a programming file. This file, once downloaded to the programmer, configures the design according to the user’s desired function


■ Lattice/Vantis Programmable Array Logic (PAL) architecture

■ Electrically-erasable CMOS technology providing half power (90 mA ICC) at high speed

  — -15 = 15-ns tPD

  — -25 = 25-ns tPD

■ Sixteen macrocells with configurable I/O architecture

■ Registered or combinatorial operation

■ Registers programmable as D, T, J-K, or S-R

■ Asynchronous clocking via product term or bank register clocking from external pins

■ Register preload for testability

■ Power-up reset for initialization

■ Space-saving 24-pin SKINNYDIP and 28-pin PLCC packages

■ Fully tested for 100% programming yield and high reliability

■ Extensive third-party software and programmer support through FusionPLD partners

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