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Lattice PALCE22V10 Family

PALCE22V10 Family

The PALCE22V10 provides user-programmable logic for replacing conventional SSI/MSI gates and flip-flops at a reduced chip count. The PALCE22V10Z is an advanced PAL device built with zero-power, high-speed, electricallyerasable CMOS technology. It provides user-programmable logic for replacing conventional zeropower CMOS SSI/MSI gates and flip-flops at a reduced chip count. The PALCE22V10Z provides zero standby power and high speed. At 30 µA maximum standby current, the PALCE22V10Z allows battery-powered operation for an extended period. The PAL device implements the familiar Boolean logic transfer function, the sum of products. The PAL device is a programmable AND array driving a fixed OR array. The AND array is programmed to create custom product terms, while the OR array sums selected terms at the outputs. The product terms are connected to the fixed OR array with a varied distribution from 8 to16 across the outputs (see Block Diagram). The OR sum of the products feeds the output macrocell. Each macrocell can be programmed as registered or combinatorial, and active-high or active low. The output configuration is determined by two bits controlling two multiplexers in each macrocell.


The PALCE22V10 allows the systems engineer to implement the design on-chip, by programming EE cells to configure AND and OR gates within the device, according to the desired logic function. Complex interconnections between gates, which previously required time-consuming layout, are lifted from the PC board and placed on silicon, where they can be easily modified during prototyping or production. The PALCE22V10Z is the zero-power version of the PALCE22V10. It has all the architectural features of the PALCE22V10. In addition, the PALCE22V10Z has zero standby power and unused product term disable. Product terms with all connections opened assume the logical HIGH state; product terms connected to both true and complement of any single input assume the logical LOW state. The PALCE22V10 has 12 inputs and 10 I/O macrocells. The macrocell (Figure 1) allows one of four potential output configurations registered output or combinatorial I/O, active high or active low (see Figure 1). The configuration choice is made according to the user’s design specification and corresponding programming of the configuration bits S0 - S1. Multiplexer controls are connected to ground (0) through a programmable bit, selecting the “0” path through the multiplexer. Erasing the bit disconnects the control line from GND and it is driven to a high level, selecting the “1” path. The device is produced with an EE cell link at each input to the AND gate array, and connections may be selectively removed by applying appropriate voltages to the circuit. Utilizing an easilyimplemented programming algorithm, these products can be rapidly programmed to any customized pattern.


◆ As fast as 5-ns propagation delay and 142.8 MHz fMAX (external)

◆ Low-power EE CMOS

◆ 10 macrocells programmable as registered or combinatorial, and active high or active low to

  match application needs

◆ Varied product term distribution allows up to 16 product terms per output for complex functions

◆ Peripheral Component Interconnect (PCI) compliant (-5/-7/-10)

◆ Global asynchronous reset and synchronous preset for initialization

◆ Power-up reset for initialization and register preload for testability

◆ Extensive third-party software and programmer support

◆ 24-pin SKINNY DIP, 24-pin SOIC, and 28-pin PLCC

◆ 5-ns and 7.5-ns versions utilize split leadframes for improved performance

PALCE22V10 Family Devices

PALCE22V10 Family Documents

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