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Lattice PALCE20V8 Family

PALCE20V8 Family

The PALCE20V8 is an advanced PAL device built with low-power, high-speed, electricallyerasable CMOS technology. Its macrocells provide a universal device architecture. The PALCE20V8 is fully compatible with the GAL20V8 and can directly replace PAL20R8 series devices and most 24-pin combinatorial PAL devices. Device logic is automatically configured according to the user’s design specification. A design is implemented using any of a number of popular design software packages, allowing automatic creation of a programming file based on Boolean or state equations. Design software also verifies the design and can provide test vectors for the finished device. Programming can be accomplished on standard PAL device programmers. The PALCE20V8 utilizes the familiar sum-of-products (AND/OR) architecture that allows users to implement complex logic functions easily and efficiently. Multiple levels of combinatorial logic can always be reduced to sum-of-products form, taking advantage of the very wide input gates available in PAL devices. The equations are programmed into the device through floating-gate cells in the AND logic array that can be erased electrically.The fixed OR array allows up to eight data product terms per output for logic functions. The sum of these products feeds the output macrocell. Each macrocell can be programmed as registered or combinatorial with an active-high or active-low output. The output configuration is determined by two global bits and one local bit controlling four multiplexers in each macrocell.


The PALCE20V8 is a universal PAL device. It has eight independently configurable macrocells (MC0-MC7). Each macrocell can be configured as a registered output, combinatorial output, combinatorial I/O, or dedicated input. The programming matrix implements a programmable AND logic array, which drives a fixed OR logic array. Buffers for device inputs have complementary outputs to provide user-programmable input signal polarity. Pins 1 and 13 serve either as array inputs or as clock (CLK) and output enable (OE) for all flip-flops. Unused input pins should be tied directly to VCC or GND. Product terms with all bits unprogrammed (disconnected) assume the logical HIGH state, and product terms with both true and complement of any input signal connected assume a logical LOW state. The programmable functions on the PALCE20V8 are automatically configured from the user’s design specification, which can be in a number of formats. The design specification is processed by development software to verify the design and create a programming file. This file, once downloaded to a programmer, configures the device according to the user’s desired function. The user is given two design options with the PALCE20V8. First, it can be programmed as an emulated PAL device. This includes the PAL20R8 series and most 24-pin combinatorial PAL devices. The PAL device programmer manufacturer will supply device codes for the standard PAL architectures to be used with the PALCE20V8. The programmer will program the PALCE20V8 to the corresponding PAL device architecture. This allows the user to use existing standard PAL device JEDEC files without making any changes to them. Alternatively, the device can be programmed directly as a PALCE20V8. Here the user must use the PALCE20V8 device code. This option provides full utilization of the macrocells, allowing non-standard architectures to be built.


◆ Pin and function compatible with all PAL 20V8 devices

◆ Electrically erasable CMOS technology provides reconfigurable logic and full testability

◆ High-speed CMOS technology

— 5-ns propagation delay for “-5” version

— 7.5-ns propagation delay for “-7” version

◆ Direct plug-in replacement for a wide range of 24-pin PAL devices

◆ Programmable enable/disable control

◆ Outputs individually programmable as registered or combinatorial

◆ Peripheral Component Interconnect (PCI) compliant

◆ Preloadable output registers for testability

◆ Automatic register reset on power-up

◆ Cost-effective 24-pin plastic SKINNY DIP and 28-pin PLCC packages

◆ Extensive third-party software and programmer support

◆ Fully tested for 100% programming and functional yields and high reliability

◆ Programmable output polarity

◆ 5-ns version utilizes a split leadframe for improved performance

PALCE20V8 Family Devices

PALCE20V8 Family Documents

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