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Lattice PALCE16V8 Family

PALCE16V8 Family

GENERAL DESCRIPTION

The PALCE16V8 is an advanced PAL device built with low-power, high-speed, electricallyerasable CMOS technology. It is functionally compatible with all 20-pin GAL devices. The macrocells provide a universal device architecture. The PALCE16V8 will directly replace the PAL16R8, with the exception of the PAL16C1. The PALCE16V8Z provides zero standby power and high speed. At 30-µA maximum standby current, the PALCE16V8Z allows battery-powered operation for an extended period. The PALCE16V8 utilizes the familiar sum-of-products (AND/OR) architecture that allows users to implement complex logic functions easily and efficiently. Multiple levels of combinatorial logic can always be reduced to sum-of-products form, taking advantage of the very wide input gates available in PAL devices. The equations are programmed into the device through floating-gate cells in the AND logic array that can be erased electrically. The fixed OR array allows up to eight data product terms per output for logic functions. The sum of these products feeds the output macrocell. Each macrocell can be programmed as registered or combinatorial with an active-high or active-low output. The output configuration is determined by two global bits and one local bit controlling four multiplexers in each macrocell.

FUNCTION DESCRIPTION

The PALCE16V8 is a universal PAL device. The PALCE16V8Z is the zero-power version of the PALCE16V8. It has all the architectural features of the PALCE16V8. In addition, the PALCE16V8Z has zero standby power and an unused product term disable feature for reduced power consumption. It has eight independently configurable macrocells (MC0-MC7). Each macrocell can be configured as registered output, combinatorial output, combinatorial I/O or dedicated input. The programming matrix implements a programmable AND logic array, which drives a fixed OR logic array. Buffers for device inputs have complementary outputs to provide userprogrammable input signal polarity. Pins 1 and 11 serve either as array inputs or as clock (CLK) and output enable (OE), respectively, for all flip-flops. Unused input pins should be tied directly to VCC or GND. Product terms with all bits unprogrammed (disconnected) assume the logical HIGH state, and product terms with both true and complement of any input signal connected assume a logical LOW state. The programmable functions on the PALCE16V8 are automatically configured from the user’s design specification. The design specification is processed by development software to verify the design and create a programming file (JEDEC). This file, once downloaded to a programmer, configures the device according to the user’s desired function. The user is given two design options with the PALCE16V8. First, it can be programmed as a standard PAL device from the PAL16R8 series. The PAL programmer manufacturer will supply device codes for the standard PAL device architectures to be used with the PALCE16V8. The programmer will program the PALCE16V8 in the corresponding architecture. This allows the user to use existing standard PAL device JEDEC files without making any changes to them.Alternatively, the device can be programmed as a PALCE16V8. Here the user must use the PALCE16V8 device code. This option allows full utilization of the macrocell.

FEATURE

◆ Pin and function compatible with all 20-pin PAL® devices

◆ Electrically erasable CMOS technology provides reconfigurable logic and full testability

◆ High-speed CMOS technology

— 5-ns propagation delay for “-5” version

— 7.5-ns propagation delay for “-7” version

◆ Direct plug-in replacement for the PAL16R8 series

◆ Outputs programmable as registered or combinatorial in any combination

◆ Peripheral Component Interconnect (PCI) compliant

◆ Programmable output polarity

◆ Programmable enable/disable control

◆ Preloadable output registers for testability

◆ Automatic register reset on power up

◆ Cost-effective 20-pin plastic DIP, PLCC, and SOIC packages

◆ Extensive third-party software and programmer support

◆ Fully tested for 100% programming and functional yields and high reliability

◆ 5-ns version utilizes a split leadframe for improved performance

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