This website uses cookies. By using this site, you consent to the use of cookies. For more information, please take a look at our Privacy Policy.
Home > FPGA Familis > Lattice MachXO3D Family


Lattice MachXO3D Family

MachXO3D Family

The MachXO3D family is the next generation of Lattice Semiconductor Low Density PLDs including enhanced  security features and on-chip dual boot flash. The enhanced security features include Advanced Encryption Standard (AES) AES-128/256, Secure Hash Algorithm (SHA) SHA-256, Elliptic Curve Digital Signature Algorithm (ECDSA), Elliptic Curve Integrated Encryption Scheme (ECIES), Hash Message Authentication Code (HMAC) HMAC-SHA256, Public Key Cryptography, and Unique Secure ID. The MachXO3D family is a Root-of-Trust hardware solution that can easily scale to protect the whole system with its enhanced bitstream security and user mode functions. 

The MachXO3D provides breakthrough I/O density with high number of options for I/O programmability. The device I/O features the support for latest industry standard I/O, including programmable slew-rate enhancements and I3C support. The MachXO3D family of low power, instanton, Flash based PLDs have two devices with densities of 4300 and 9400 Look-Up Tables (LUTs). MachXO3D devices include on-chip dual boot configuration flash as well as multi-sectored User Flash Memory (UFM). Inaddition to LUT-based programmable logic, these devices feature Embedded Block RAM (EBR), Distributed RAM, Locked Loops (PLLs), pre-engineered source synchronous I/O support, advanced configuration support including on-chip dual-boot capability and hardened versions of commonly used functions such as SPI controller, I2C controller, and timer/counter. 

The MachXO3D are designed on a 65-nm non-volatile low power process. The device architecture has several features such as programmable low swing differential I/O and the ability to turn off I/O banks, on-chip PLLs and oscillators dynamically. These features help manage static and dynamic power consumption resulting in low power for all members of the family. 


1.1.1. Solutions

 Best-In-Class control PLD with advanced security

  functions, provide secure/authenticated boot and

  root of trust function

 Optimized footprint, logic density, I/O count, I/O

  performance devices for I/O management and

  logic applications

 High I/O logic, high I/O devices for I/O expansion


1.1.2. Flexible Architecture

 Logic Density ranging from 4.3K to 9.4K LUT4

 High I/O to LUT ratio with up to 383 I/O pins

1.1.3. Dedicated Embedded Security Block

 Advanced Encryption Standard (AES): AES-128/256 Encryption/Decryption

 Secure Hash Algorithm (SHA): SHA-256

 Elliptic Curve Digital Signature Algorithm (ECDSA): ECDSA-based authentication

 Hash Message Authentication Code (HMAC): HMAC-SHA256

 Elliptic Curve Integrated Encryption Scheme (ECIES): ECIES Encryption and Decryption

 True Random Number Generator (TRNG)

 Key Management using Elliptic Curve DiffieHellman (ECDH) Public Key Cryptography

 Unique Secure ID

 Guard against malicious attacks

 Interface for user logic via WISHBONE and High Speed Port (HSP)

 Federal Information Processing Standard (FIPS) supported Security Protocols

1.1.4. Pre-Engineered Source Synchronous I/O

 DDR registers in I/O cells

 Dedicated gearing logic

 7:1 Gearing for Display I/O

 Generic DDR, DDRx2, DDRx4 1.1.5. High Performance, Flexible I/O Buffer

 Programmable sysI/OTM buffer supports wide range of interfaces:

 LVCMOS 3.3/2.5/1.8/1.5/1.2



 MIPI D-PHY Emulated

 Schmitt trigger inputs, up to 0.5 V hysteresis

 Ideal for I/O bridging applications

 I3C compatible on selective I/O

 Slew rate control as Slow/Fast

 I/O support hot socketing

 On-chip differential termination

 Programmable pull-up or pull-down mode

1.1.6. Flexible On-Chip Clocking

 Eight primary clocks

 Up to two edge clocks for high-speed I/O interfaces (top and bottom sides only)

 Two analog PLLs per device with fractional-n frequency synthesis

 Wide input frequency range (7 MHz to 400 MHz).

1.1.7. Non-volatile, Reconfigurable

 Instant-on

 Powers up in microseconds

 On-chip dual boot

 Multi-sectored UFM for customer data storage

 Single-chip, secure solution

 Programmable through JTAG, SPI or I2C

 Reconfigurable Flash

 Supports background programming of non-volatile memory

1.1.8. TransFR Reconfiguration

 In-field logic update while I/O holds the system state

1.1.9. Enhanced System Level Support

 On-chip hardened functions: SPI, I2C, and timer/counter

 On-chip oscillator with 5.5% accuracy

 Unique TraceID for system tracking

 Single power supply with extended operating range

 IEEE Standard 1149.1 boundary scan

 IEEE 1532 compliant in-system programming

1.1.10. Advanced Packaging

 0.5 mm pitch: 4.3K to 9.4K densities with up to 58 I/O in QFN packages

 0.8 mm pitch: 4.3K to 9.4K densities with up to 383 I/O in BGA packages

 Pin-compatible with MachXO3LF product family of devices

1.1.11. Applications

 Secure boot and Root of Trust

 Consumer Electronics

 Compute and Storage

 Wireless Communications

 Industrial Control Systems

 Automotive System 

MachXO3D Family Documents

Need Help?


If you have any questions about the product and related issues, Please contact us.