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Lattice MachXO Family

MachXO Family


The MachXO family architecture contains an array of logic blocks surrounded by Programmable I/O (PIO). Some devices in this family have sysCLOCK PLLs and blocks of sysMEM Embedded Block RAM (EBRs). Figures 2-1, 2-2, and 2-3 show the block diagrams of the various family members. The logic blocks are arranged in a two-dimensional grid with rows and columns. The EBR blocks are arranged in a column to the left of the logic array. The PIO cells are located at the periphery of the device, arranged into Banks. The PIOs utilize a flexible I/O buffer referred to as a sysIO interface that supports operation with a variety of interface standards. The blocks are connected with many vertical and horizontal routing channel resources. The place and route software tool automatically allocates these routing resources. There are two kinds of logic blocks, the Programmable Functional Unit (PFU) and the Programmable Functional unit without RAM (PFF). The PFU contains the building blocks for logic, arithmetic, RAM, ROM, and register functions. The PFF block contains building blocks for logic, arithmetic, ROM, and register functions. Both the PFU and PFF blocks are optimized for flexibility, allowing complex designs to be implemented quickly and effectively. Logic blocks are arranged in a two-dimensional array. Only one type of block is used per row. In the MachXO family, the number of sysIO Banks varies by device. There are different types of I/O Buffers on different Banks. See the details in later sections of this document. The sysMEM EBRs are large, dedicated fast memory blocks; these blocks are found only in the larger devices. These blocks can be configured as RAM, ROM or FIFO. FIFO support includes dedicated FIFO pointer and flag “hard” control logic to minimize LUT use. The MachXO registers in PFU and sysI/O can be configured to be SET or RESET. After power up and device is configured, the device enters into user mode with these registers SET/RESET according to the configuration setting, allowing device entering to a known state for predictable system function. The MachXO architecture provides up to two sysCLOCK Phase Locked Loop (PLL) blocks on larger devices. These blocks are located at either end of the memory blocks. The PLLs have multiply, divide, and phase shifting capabilities that are used to manage the frequency and phase relationships of the clocks. Every device in the family has a JTAG Port that supports programming and configuration of the device as well as access to the user logic. The MachXO devices are available for operation from 3.3 V, 2.5 V, 1.8 V, and 1.2 V power supplies, providing easy integration into the overall system.


 Non-volatile, Infinitely Reconfigurable

• Instant-on – powers up in microseconds

• Single chip, no external configuration memory required

• Excellent design security, no bit stream to intercept

• Reconfigure SRAM based logic in milliseconds

• SRAM and non-volatile memory programmable through JTAG port

• Supports background programming of non-volatile memory

 Sleep Mode

• Allows up to 100x static current reduction

 TransFR Reconfiguration (TFR)

• In-field logic update while system operates

 High I/O to Logic Density

• 256 to 2280 LUT4s

• 73 to 271 I/Os with extensive package options

• Density migration supported

• Lead free/RoHS compliant packaging

 Embedded and Distributed Memory

• Up to 27.6 Kbits sysMEM Embedded Block RAM

• Up to 7.7 Kbits distributed RAM

• Dedicated FIFO control logic

 Flexible I/O Buffer

• Programmable sysIO buffer supports wide range of interfaces:

— LVCMOS 3.3/2.5/1.8/1.5/1.2





• Up to two analog PLLs per device

• Clock multiply, divide, and phase shifting

 System Level Support

• IEEE Standard 1149.1 Boundary Scan

• Onboard oscillator

• Devices operate with 3.3 V, 2.5 V, 1.8 V or 1.2 V power supply

• IEEE 1532 compliant in-system programming

MachXO Family Devices

MachXO Family Documents

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