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Lattice LatticeXP Family

LatticeXP Family

The LatticeXP architecture contains an array of logic blocks surrounded by Programmable I/O Cells (PIC). Interspersed between the rows of logic blocks are rows of sysMEM Embedded Block RAM (EBR) as shown in Figure 2- 1. On the left and right sides of the PFU array, there are Non-volatile Memory Blocks. In configuration mode this nonvolatile memory is programmed via the IEEE 1149.1 TAP port or the sysCONFIG™ peripheral port. On power up, the configuration data is transferred from the Non-volatile Memory Blocks to the configuration SRAM. With this technology, expensive external configuration memories are not required and designs are secured from unauthorized read-back. This transfer of data from non-volatile memory to configuration SRAM via wide busses happens in microseconds, providing an “instant-on” capability that allows easy interfacing in many applications. There are two kinds of logic blocks, the Programmable Functional Unit (PFU) and Programmable Functional unit without RAM/ROM (PFF). The PFU contains the building blocks for logic, arithmetic, RAM, ROM and register functions. The PFF block contains building blocks for logic, arithmetic and ROM functions. Both PFU and PFF blocks are optimized for flexibility, allowing complex designs to be implemented quickly and efficiently. Logic Blocks are arranged in a two-dimensional array. Only one type of block is used per row. The PFU blocks are used on the outside rows. The rest of the core consists of rows of PFF blocks interspersed with rows of PFU blocks. For every three rows of PFF blocks there is a row of PFU blocks. Each PIC block encompasses two PIOs (PIO pairs) with their respective sysIO interfaces. PIO pairs on the left and right edges of the device can be configured as LVDS transmit/receive pairs. sysMEM EBRs are large dedicated fast memory blocks. They can be configured as RAM or ROM. The PFU, PFF, PIC and EBR Blocks are arranged in a two-dimensional grid with rows and columns as shown in Figure 2-1. The blocks are connected with many vertical and horizontal routing channel resources. The place and route software tool automatically allocates these routing resources. At the end of the rows containing the sysMEM Blocks are the sysCLOCK Phase Locked Loop (PLL) Blocks. These PLLs have multiply, divide and phase shifting capability; they are used to manage the phase relationship of the clocks. The LatticeXP architecture provides up to four PLLs per device. Every device in the family has a JTAG Port with internal Logic Analyzer (ispTRACY) capability. The sysCONFIG port which allows for serial or parallel device configuration. The LatticeXP devices are available for operation from 3.3V, 2.5V, 1.8V and 1.2V power supplies, providing easy integration into the overall system.

Features

 Non-volatile, Infinitely Reconfigurable

• Instant-on – powers up in microseconds

• No external configuration memory

• Excellent design security, no bit stream to intercept

• Reconfigure SRAM based logic in milliseconds

• SRAM and non-volatile memory programmable through system configuration and JTAG ports

 Sleep Mode

• Allows up to 1000x static current reduction

 TransFR™ Reconfiguration (TFR)

• In-field logic update while system operates

 Extensive Density and Package Options

• 3.1K to 19.7K LUT4s

• 62 to 340 I/Os

• Density migration supported

 Embedded and Distributed Memory

• 54 Kbits to 396 Kbits sysMEM™ Embedded Block RAM

• Up to 79 Kbits distributed RAM

• Flexible memory resources:

 Distributed and block memory

 Flexible I/O Buffer

• Programmable sysIO™ buffer supports wide range of interfaces:

 LVCMOS 3.3/2.5/1.8/1.5/1.2

 LVTTL

– SSTL 18 Class I

 SSTL 3/2 Class I, II

– HSTL15 Class I, III

 HSTL 18 Class I, II, III

 PCI

 LVDS, Bus-LVDS, LVPECL, RSDS

 Dedicated DDR Memory Support

• Implements interface up to DDR333 (166MHz)

 sysCLOCK™ PLLs

• Up to 4 analog PLLs per device

• Clock multiply, divide and phase shifting

 System Level Support

• IEEE Standard 1149.1 Boundary Scan, plus ispTRACY™ internal logic analyzer capability

• Onboard oscillator for configuration

• Devices operate with 3.3V, 2.5V, 1.8V or 1.2V power supply

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