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Lattice LatticeSC/M Family flexiPCS

LatticeSC/M Family flexiPCS

The LatticeSC family of FPGA combines a high-performance FPGA fabric, high-performance I/Os and large embedded RAM in a single industry leading architecture. All LatticeSC devices also feature up to 32 channels of embedded SERDES with associated Physical Coding Sublayer (PCS) logic. The flexiPCS logic can be configured to support numerous industry standard high-speed data transfer protocols. Each channel of flexiPCS logic contains dedicated transmit and receive SERDES for high-speed full-duplex serial data transfers at data rates up to 3.8 Gbps. The PCS logic in each channel can be configured to support an array of popular data protocols including SONET (STS-12/STS-12c, STS-48/STS-48c, and TFI-5 support of 10 Gbps or above), Gigabit Ethernet (compliant to the IEEE 1000BASE-X specification), 1.02 or 2.04 Gbps Fibre Channel, PCI Express, and Serial RapidIO. In addition, the protocol based logic can be fully or partially bypassed in a number of configurations to allow users flexibility in designing their own high-speed data interface. Protocols requiring data rates above 3.8 Gbps can be accommodated by dedicating either one pair or all 4 channels in one PCS quad block to one data link. One quad can support full-duplex serial data transfers at data rates up to 15.2 Gbps. A single PCS quad can be configured to support 10Gb Ethernet (with a fully compliant XAUI interface), 10Gb Fibre Channel, and x4 PCI Express and 4x RapidIO. The PCS also provides bypass modes that allow a direct 8-bit or 10-bit interface from the SERDES to the FPGA logic. Each SERDES pin can also be independently DC coupled and can allow for both high-speed and low-speed operation on the same SERDES pin for such applications as Serial Digital Video.

LatticeSC/M Family flexiPCS Devices

LatticeSC/M Family flexiPCS Documents

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