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Lattice LatticeECP/EC Family

LatticeECP/EC Family


The LatticeECP/EC family of FPGA devices is optimized to deliver mainstream FPGA features at low cost. For maximum performance and value, the LatticeECP (EConomy Plus) FPGA concept combines an efficient FPGA fabric with high-speed dedicated functions. Lattice’s first family to implement this approach is the LatticeECPDSP (EConomy Plus DSP) family, providing dedicated high-performance DSP blocks on-chip. The LatticeEC (EConomy) family supports all the general purpose features of LatticeECP devices without dedicated function blocks to achieve lower cost solutions. The LatticeECP/EC FPGA fabric, which was designed from the outset with low cost in mind, contains all the critical FPGA elements: LUT-based logic, distributed and embedded memory, PLLs and support for mainstream I/Os. Dedicated DDR memory interface logic is also included to support this memory that is becoming increasingly prevalent in cost-sensitive applications. The ispLEVER design tool suite from Lattice allows large complex designs to be efficiently implemented using the LatticeECP/EC FPGA family. Synthesis library support for LatticeECP/EC is available for popular logic synthesis tools. The ispLEVER tool uses the synthesis tool output along with the constraints from its floor planning tools to place and route the design in the LatticeECP/EC device. The ispLEVER tool extracts the timing from the routing and back-annotates it into the design for timing verification. Lattice provides many pre-designed IP (Intellectual Property) ispLeverCORE modules for the LatticeECP/EC family. By using these IPs as standardized blocks, designers are free to concentrate on the unique aspects of their design, increasing their productivity


 Extensive Density and Package Options

• 1.5K to 32.8K LUT4s

• 65 to 496 I/Os

• Density migration supported

 sysDSP Block (LatticeECP Versions)

• High performance multiply and accumulate

• 4 to 8 blocks

 4 to 8 36x36 multipliers or

– 16 to 32 18x18 multipliers or

 32 to 64 9x9 multipliers

 Embedded and Distributed Memory

• 18 Kbits to 498 Kbits sysMEM Embedded Block RAM (EBR)

• Up to 131 Kbits distributed RAM

• Flexible memory resources:

 Distributed and block memory

 Flexible I/O Buffer

• Programmable sysI/O buffer supports wide range of interfaces:

 LVCMOS 3.3/2.5/1.8/1.5/1.2


 SSTL 3/2 Class I, II, SSTL18 Class I

 HSTL 18 Class I, II, III, HSTL15 Class I, III



 Dedicated DDR Memory Support

• Implements interface up to DDR400 (200MHz)


• Up to four analog PLLs per device

• Clock multiply, divide and phase shifting

 System Level Support

• IEEE Standard 1149.1 Boundary Scan, plus ispTRACY internal logic analyzer capability

• SPI boot flash interface

• 1.2V power supply

 Low Cost FPGA

• Features optimized for mainstream applications

• Low cost TQFP and PQFP packaging

LatticeECP/EC Family Devices

LatticeECP/EC Family Documents

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