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Lattice ispXPLD 5000MX Family

ispXPLD 5000MX Family

Description

These devices extend the capability of Lattice’s popular SuperWIDE CPLD architecture by providing flexible memory capability and the ability to trade-off memory and logic resources within the device. The family supports single-port SRAM, true dual-port SRAM, FIFO, and ternary CAM operation. In addition, sysCLOCK PLLs and sysIO interfaces provide support to maximize system-level performance.The devices provide designers with a convenient one-chip solution that provides logic availability at bootup, design security, and extreme reconfigurability. The use of advanced process technology provides industry-leading performance with combinatorial propagation delay as low as 4.0ns, 2.8ns clock-to-out delay, 2.5ns set-up time, and operating frequency up to 285MHz. This performance is coupled with low static and dynamic power consumption. The ispXPLD 5000MX architecture provides predictable deterministic timing. The availability of 3.3, 2.5 and 1.8V versions of these devices (designated the 5000MV, 5000MB and 5000MC series, respectively), along with the flexibility of the sysIO interface, helps users meet the challenge of today’s mixed voltage designs. Boundary scan testability further eases integration into today’s complex systems. A variety of density and package options increase the likelihood of a good fit for a particular application. Table 1 shows the members of the ispXPLD 5000MX family. The ispXPLD 5000MX family has been designed to ensure that different density devices in the same package have compatible pin-outs. Furthermore, the architecture ensures a high success rate when performing design migration from lower density parts to higher density parts.

Functional

The mix of system-level functionality, memory and logic allows the ispXPLD devices to address mainstream system functions previously relegated only to FPGAs or ASICs. The ability to integrate multiple independent blocks of buffer memory using a variety of memory architectures (FIFO, dual-port, CAM, etc.) together with fast programmable logic onto a single device offers great application flexibility. The addition of programmable sysIO interface standard support and sysCLOCK high-performance clocking amplifies the value of the devices as efficient control and data conductors within leading-edge systems. Potential application areas include high-performance bus bridges, intelligent backplane interfaces, protocol processors and the like. The architecture builds upon traditional CPLD strengths and addresses high-density, high-performance (up to 285 MHz) applications for industries requiring fast time to market. These industries include telecommunications, data communications and data processing. Typical applications in telecommunications include switches, exchange equipment, and cellular base stations; in data communications, high-end routers, bridges, switches, repeaters and intelligent hubs; and, in data processing, disk-array systems, data storage, RAID controllers, high-end graphics, high-end servers, scanners and imaging systems.

Feature

The two largest segments of the high density programmable logic market have traditionally been nonvolatile, Complex Programmable Logic Devices (CPLDs) and SRAM-based Field  Programmable Gate Arrays (FPGAs). CPLDs have historically provided the benefits of

ƒ Fast, predictable timing

ƒ Single-level wide logic support

ƒ Non-volatile, in-system programmability (ISP)

ƒ "Instant on" operation while SRAM-based FPGAs have provided

ƒ Very high logic density

ƒ On-chip Memory Support

ƒ Unlimited in-system reconfigurability

ƒ Low standby power

Lattice Semiconductor has developed a logical successor to earlier Simple PLD and Complex PLD architectures, called the ispXPLD (eXpanded Programmable Logic Device), that combines the best attributes of CPLDs and FPGAs in a single architecture. These new devices are based upon a convergence of programming technology and architecture that is truly unique. The new programming technology, called ispXP (for in-system programmable eXpanded Programmability), provides non-volatile in-system programmability combined with reconfigurability via a

microprocessor sysCONFIG port. The new architecture, based on a set of homogeneous Multi-FunctionBlocks that can implement a variety of functions based on the user's application requirements, supports both logic and memory on-chip with up to 300K system gates in a single device. In addition, extremely wide functions of up to 136 inputs can be implemented in a single level of logic for wide parallel logic processing.

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