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Lattice ispPAC-POWR Family

ispPAC-POWR Family

Lattice ispPAC-POWR devices provide highly accurate, flexible, and low cost solutions for circuit board power supply and processor/DSP supply management. By integrating a versatile PLD core with Analog-to-Digital (ADC) converter, Digital-to-Analog Converters (DAC), differential sense analog monitors, I2C communication, and insystem programmability (isp), Lattice power management devices increase board reliability, decrease component count, and help cut costs. Two power management families: ProcessorPM and Power Manager II address a variety of applications – all in a single low-cost chip. The ispPAC-POWR product family is built on EE8A which is a 3.3V shallow trench isolated, 0.35um drawn / 0.25um Leff CMOS process with Electrically Erasable (E2) cells. This process uses three planarized metal interconnect layers and single layer polysilicon fabricated at either United Microelectronics Company (UMC) wafer fab, or Epson wafer fab at Sakata, and assembled at Advance Semiconductor Engineering Malaysia (ASEM), Amkor Korea and UNISEM Group Singapore, in TQFP and QFNS packages. To verify product reliability, Lattice Semiconductor maintains an active Early Life and Inherent Life Reliability Monitor program on the ispPAC-POWR products. Lattice Semiconductor publishes the Reliability Monitor Data quarterly

ispPAC-POWR Family Documents

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