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Lattice ISPPAC Family



Lattice’s Power Manager II LA-ispPAC-POWR1014/A is a general-purpose power-supply monitor and sequence controller, incorporating both in-system programmable logic and in-system programmable analog functions implemented in non-volatile E2 CMOS technology. The LA-ispPAC-POWR1014/A device provides 10 independent analog input channels to monitor up to 10 power supply test points. Each of these input channels has two independently programmable comparators to support both high/low and in-bounds/out-of-bounds (window-compare) monitor functions. Four general-purpose digital inputs are also provided for miscellaneous control functions. The LA-ispPAC-POWR1014/A provides 14 open-drain digital outputs that can be used for controlling DC-DC converters, low-drop-out regulators (LDOs) and optocouplers, as well as for supervisory and general-purpose logic interface functions. Two of these outputs (HVOUT1-HVOUT2) may be configured as high-voltage MOSFET drivers. In high-voltage mode these outputs can provide up to 8V for driving the gates of n-channel MOSFETs so that they can be used as high-side power switches controlling the supplies with a programmable ramp rate for both ramp up and ramp down. The LA-ispPAC-POWR1014/A incorporates a 24-macrocell CPLD that can be used to implement complex state machine sequencing for the control of multiple power supplies as well as combinatorial logic functions. The status of all of the comparators on the analog input channels as well as the general purpose digital inputs are used as inputs by the CPLD array, and all digital outputs may be controlled by the CPLD. Four independently programmable timers can create delays and time-outs ranging from 32µs to 2 seconds. The CPLD is programmed using LogiBuilder, an easy-to-learn language integrated into the PAC-Designer software. Control sequences are written to monitor the status of any of the analog input channel comparators or the digital inputs. The on-chip 10-bit A/D converter is used to monitor the VMON voltage through the I2 C bus or JTAG interface of the LA-ispPAC-POWR1014A device. The I2 C bus/SMBus interface allows an external microcontroller to measure the voltages connected to the VMON inputs, read back the status of each of the VMON comparator and PLD outputs, control logic signals IN2 to IN4 and control the output pins (LA-ispPAC-POWR1014A only). The JTAG interface can be used to read out all I2 C registers during manufacturing.


 Monitor and Control Multiple Power Supplies

• Simultaneously monitors up to 10 power supplies

• Provides up to 14 output control signals

• Programmable digital and analog circuitry

 AEC-Q100 Tested and Qualified

 Embedded PLD for Sequence Control

• 24-macrocell CPLD implements both statemachines and combinatorial logic functions

 Embedded Programmable Timers

• Four independent timers

• 32µs to 2 second intervals for timing sequences

 Analog Input Monitoring

• 10 independent analog monitor inputs

• Two programmable threshold comparators peranalog input

• Hardware window comparison

• 10-bit ADC for I2C monitoring (LA-ispPACPOWR1014A only)

 High-Voltage FET Drivers

• Power supply ramp up/down control

• Programmable current and voltage output

• Independently configurable for FET control or digital output

 2-Wire (I2C/SMBus Compatible) Interface

• Comparator status monitor

• ADC readout

• Direct control of inputs and outputs

• Power sequence control

• Only available with LA-ispPAC-POWR1014A

 3.3V Operation, Wide Supply Range 2.8V to 3.96V

• Automotive temperature range: -40°C to +105°C

• 48-pin TQFP package, lead-free option

 Multi-Function JTAG Interface

• In-system programming

• Access to all I2C registers

• Direct input control 

ISPPAC Family Documents

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