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Lattice ispMACH 5000VG Family

ispMACH 5000VG Family

The ispMACH 5000VG represents the third generation of Latticeā€™s SuperWIDE CPLD architecture. Through their wide 68-input blocks, these devices give significantly improved speed performance for typical designs over architectures with fewer inputs. 

The ispMACH 5000VG takes the unique benefits of the SuperWIDE architecture and extends it to higher densities referred to as SuperBIG, by using the combination of an innovative product term architecture and a twotiered hierarchical routing architecture. Additionally, sysCLOCK and sysIO capabilities have been added to maximize system-level performance and integration.

The ispMACH 5000VG devices consist of multiple SuperWIDE 68-input, 32-macrocell Generic Logic Blocks (GLBs) interconnected by a tiered routing system. Figure 1 shows the functional block diagram of the ispMACH 5000VG. Groups of four GLBs, referred to as segments, are interconnected via a Segment Routing Pool (SRP). Segments are interconnected via the Global Routing Pool (GRP.) Together the GLBs and the routing pools allow designers to create large designs in a single device without compromising performance.

Each GLB has 68 inputs coming from the SRP and contains 163 product terms. These product terms form groups of five product term clusters, which feed the PT sharing array or the macrocell directly. The ispMACH 5000VG allows up to 160 product terms to be connected to a single macrocell via the product term expanders and PT Sharing Array. 

The macrocell is designed to provide flexible clocking and control functionality with the capability to select between global, product term and block-level resources. The outputs of the macrocells are fed back into the switch matrices and, if required, the sysIO cell.

ispMACH 5000VG Family Documents

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