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Home > FPGA Familis > Lattice ispGDX 160V/VA


Lattice ispGDX 160V/VA

ispGDX 160V/VA


found in each I/O cell. Each output has individual, pro-grammable /O tri-state control (OE), output latch clock(CLK), clock enable (CLKEN), and two multiplexer con-trol (MUX0 and MUX1) inputs. Polarity for these signals is programmable for each I/0 cell. The MUX0 and MUX1 inputs control a fast 4:1 MUX, allowing dynamic selection of up to four signal sources for a given output. A wider 16:1 MUX can be implemented with the MUX expander feature of each I/O and a propagation delay increase of 2.0ns. OE, CLK, CL KEN, and MUX0 and MUX1 inputs can be driven directly from selected sets of I/O pins. Optional dedicated clock input pins give minimum clock- to-output delays. CLK and CLKEN share the same set of I/O pins. CLKEN disables the register clock when CLKEN= 0. Through in-system programming, connections between I/O pins and architectural features (latched or registered inputs or outputs, output enable control, etc.) can be defined. In keeping with its data path application focus,the ispGDXV devices contain no programmable logic arrays. All input pins include Schmitt trigger buffers for noise immunity. These connections are programmed into the device using non-volatile E?CMOS technology. Non-volatile technology means the device configuration is saved even when the power jis removed from the device.

In addition, there are no pin-to-pin routing constraints for 1:1 or 1:n signal routing. That is, any l/0 pin configured as an input can drive one or more 1/0 pins configured as outputs. The device pins also have the ability to set outputs to fixed HIGH or LOW logic levels (Jumper or DIP Switch mode). Device outputs are specified for 24mA sink and 12mA source current (at JEDEC LVTTL levels) and can be tied together in parallel for greater drive. On the ispGDXVA, each /o pin is individually programmable for 3.3V or 2.5V output levels as described later. Program- mable output slew rate control can be defined independently for each l/0 pin tol reduce overall ground bounce and switching noise. AlI /0 pins are equipped with IEEE1149. 1-compliant Boundary Scan Test circuitry for enhanced testbility. In addition, in-system. programming is supported through the Test Access Port via a special set of private com-mands. The ispGDXV 1/Os are designed to withstand "Iive inser-tion" system environments. The /O buffers are disabled during power-up and power-down cycles. When design- ingfor"live insertion,' absolute maximum rating conditions

for the Vco and I/O pins must still be met.



  一Advanced Architecture Addresses Programmable PCB Interconnect, Bus Interface Integration and Jumper/Switch Replacement

  一“Any Input to Any Output" Routing

  - , Fixed HIGH or LOW Output Option for Jumper/DIP

  Switch Emulation

  - Space-Saving PQFP and BGA Packaging

  - Dedicated IEEE 1149.1-Compliant Boundary ScanTest .


  一3.3V Core Power Supply

  一3.5ns Input-to-Output/3.5ns Clock-to-Output Delay*

  250MHz Maximum Clock Frequency*

  一TTL/3.3V/2.5V Compatible Input Thresholds and

  Output Levels (Individually Programmable)"

  一Low-Power: 16.5mA Quiescent Icc"

  一. 24mA loL Drive with Programmable Slew RateControl Option

  - PCI Compatible Drive Capability*

  Schmitt Trigger Inputs for Noise Immunity

  Electrically Erasable and Reprogrammable

  Non-Volatile E'CMOS Technology


  一3.3V In-System Programmable Using Boundary Scan.Test Access Port (TAP)

  一Change Interconnects in Seconds


  一Combinatorial/Latched/Registered Inputs or Outputs

  一Individual /0 Tri-state Control with Polarity Control Dedicated Clock/Clock Enable Input Pins (four) O

  Programmable Clocks/Clock Enables from 1/0 Pins(40)

  - Single Level 4:1 Dynamic Path Selection (Tpd = 3.5ns)

  Programmable Wide-MUX Cascade Feature

  Supports up to 16:1 mUX

  Programmable Pull-ups, Bus HoldLatch and Open

  Drain on 10 Pins

  一Outputs Tri-state During Power-up ("Live Insertion"



●“VA" Version Only

ispGDX 160V/VA Devices

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