Configuration is the process of loading a design via a bitstream file into the FPGA internal configuration memory. Readback is the process of reading the configuration data in a programmed FPGA back out, into a file. This application note is segmented into three main sections: Configuration Modes, Bit Generation Options, and Configuration Process and Flow. The Configuration Modes Section shows all the different modes with schematic diagrams, functional timing waveforms, and descriptions. The Bit Generation Options section describes the options available when creating a bitstream file with the ispLEVER Bitstream Data Generator software program; this section also shows the configuration frame format and content. The Configuration Process and Flow section details the states of operation of the device during configuration, miscellaneous configuration options, configuration frame sizes, and bitstream file error responses. This document does not contain any configuration performance timing numbers for devices. Refer to the ORCA Series 4 Data Sheet for timing numbers.
ORSO42G5 FPGA ORCA Series 4 Family Data sheetDocument Type: Data Sheets Jul 13, 2020
ORSO82G5 FPGA ORCA Series 4 Family Data sheetDocument Type: Data Sheets Jul 13, 2020
ORT42G5 FPGA ORCA Series 4 Family Data sheetDocument Type: Data Sheets Jul 13, 2020
ORT82G5 FPGA ORCA Series 4 Family Data sheetDocument Type: Data Sheets Jul 13, 2020