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Lattice CrossLink-NX Family

CrossLink-NX Family

CrossLink™-NX family of low-power FPGAs can be used in a wide range of applications, and are optimized for bridging and processing needs in Embedded Vision applications – supporting a variety of high bandwidth sensor and display interfaces, video processing and machine learning inferencing. It is built on Lattice Nexus FPGA platform, using low-power 28 nm FD-SOI technology. It combines the extreme flexibility of an FPGA with the low power and high reliability (due to extremely low SER) of FD-SOI technology, and offers small footprint package options. CrossLink-NX supports a variety of interfaces including MIPI D-PHY (CSI-2, DSI), LVDS, SLVS, subLVDS, PCI Express (Gen1, Gen2), SGMII (Gigabit Ethernet), and more. Processing features of CrossLink-NX include up to 39K Logic Cells, 56 18x18 multipliers, 2.9 Mb of embedded memory (consisting of EBR and LRAM blocks), distributed memory, DRAM interfaces (supporting DDR3, DDR3L, LPDDR2, LPDDR3 up to 1066 Mbps x 16 data width), and ALU building blocks for soft processor. CrossLink-NX FPGAs support fast configuration of its reconfigurable SRAM-based logic fabric, ultra-fast configuration (in under 3 ms) of its programmable sysI/O™ and TransFR™ field upgrade feature. Security features to secure user designs include bitstream encryption and password protection. In addition to the high reliability inherent to FD-SOI technology (due to its extremely low SER), active reliability features such as built-in frame-based SED/SEC (for SRAM-based logic fabric), and ECC (for EBR and LRAM) are also supported. Built-in ADC is available in each device for system monitoring functions. Lattice Radiant® design software allows large complex user designs to be efficiently implemented on CrossLink-NX FPGA family. Synthesis library support for CrossLink-NX devices is available for popular logic synthesis tools. Radiant tools use the synthesis tool output along with constraints from its floor planning tools, to place and route the user design in CrossLinkNX device. The tools extract timing from the routing, and back-annotate it into the design for timing verification. Lattice provides many pre-engineered IP (Intellectual Property) modules for CrossLink-NX family. By using these configurable soft IP cores as standardized blocks, you are free to concentrate on the unique aspects of your design, increasing your productivity.


 Programmable Architecture

 17K to 39K logic cells

 24 to 56 18 x 18 multipliers (in sysDSP™blocks)

 2.5 to 2.9 Mb of embedded memory blocks(EBR, LRAM)

 36 to 192 programmable sysI/O (HighPerformance and Wide Range I/O)


 Up to two hardened 4-lane MIPI D-PHYinterfaces

 Up to 8 lanes total

 Transmit or receive

 Supports CSI-2, DSI

 20 Gbps aggregate bandwidth

 2.5Gbps per lane, 10 Gbps per D-PHYinterface

 Additional Soft D-PHY interfaces supported byHigh Performance (HP) sysI/O

 Transmit or receive

 Supports CSI-2, DSI

 Up to 1.5 Gbps per lane

 Programmable sysI/O supports wide variety ofinterfaces

 High Performance (HP) on bottom I/O dualrank

 Supports up to 1.8 V VCCIO

 Mixed voltage support (1.0 V, 1.2 V, 1.5 V,1.8 V)

 High-speed differential up to 1.5 Gbps

 Supports soft D-PHY (Tx/Rx), LVDS 7:1(Tx/Rx), SLVS (Tx/Rx), subLVDS (Rx)

 Supports SGMII (Gb Ethernet) – 2channels (Tx/Rx) at 1.25 Gbps

 Dedicated DDR3/DDR3L andLPDDR2/LPDDR3 memory support withDQS logic, up to 1066 Mbps data-     rate and x16 data-width

 Wide Range (WR) on Left, Right and Top I/OBanks

 Supports up to 3.3 V VCCIO

 Mixed voltage support (1.2 V, 1.5 V, 1.8 V,2.5 V, 3.3 V)

 Programmable slew rate (slow, med, fast)

 Controlled impedance mode

 Emulated LVDS support

 Hot-socketing

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