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Lattice CrossLink FPGA Family

CrossLink FPGA Family

CrossLink from Lattice Semiconductor is a programmable video bridging device that supports a variety of protocols and interfaces for mobile image sensors and displays. The device is based on Lattice mobile FPGA 40-nm technology. It combines the extreme flexibility of an FPGA with the low power, low cost and small footprint of an ASIC. CrossLink supports video interfaces including MIPI DPI, MIPI DBI, CMOS camera and display interfaces, OpenLDI, FPD-Link, FLATLINK, MIPI D-PHY, MIPI CSI-2, MIPI DSI, SLVS200, subLVDS, HiSPi and more. Lattice Semiconductor provides many pre-engineered IP (Intellectual Property) modules for CrossLink. 

By using these configurable soft core IPs as standardized blocks, designers are free to concentrate on the unique aspects of their design, increasing their productivity. The Lattice Diamond design software allows large complex designs to be efficiently implemented using CrossLink. Synthesis library support for CrossLink devices is available for popular logic synthesis tools. The Diamond tools use the synthesis tool output along with the constraints from its floor planning tools to place and route the design in the CrossLink device. 

CrossLink FPGA.png

The tools extract the timing from the routing and back-annotate it into the design for timing verification. Interfaces on CrossLink provide a variety of bridging solutions for smart phone, tablets, wearables, VR, AR, Drone, Smart Home, HMI as well as adjacent ISM markets. The device is capable of supporting high-resolution, high-bandwidth content for mobile cameras and displays at 4 UHD and beyond.


 Ultra-low power

 Sleep Mode Support

 Normal Operation – From 5 mW to 150 mW

 Ultra small footprint packages

 36-ball WLCSP (6 mm2)

 64-ball ucfBGA (12 mm2)

 80-ball ctfBGA (42 mm2)

 80-ball ckfBGA (49 mm2)

 81-ball csfBGA (20 mm2)

 Programmable architecture

 5936 LUTs

 180 Kb block RAM

 47 Kb distributed RAM

 Two hardened 4-lane MIPI D-PHY interfaces

 Transmit and receive

 6 Gb/s per D-PHY interface

 Programmable source synchronous I/O

 MIPI D-PHY Rx, LVDS Rx, LVDS Tx, subLVDS Rx,SLVS200 Rx, HiSPi Rx

 Up to 1200 Mb/s per I/O

 Four high-speed clock inputs

 Programmable CMOS I/O


 3.3 V, 2.5 V, 1.8 V and 1.2 V (outputs)

 LVCMOS differential outputs

 Flexible device configuration

 One Time Programmable (OTP) non-volatile configuration memory

 Master SPI boot from external flash

 Dual image booting supported

 I2C programming

 SPI programming

 TransFR I/O for simple field updates

 Enhanced system level support

 Reveal logic analyzer

 TraceID for system tracking

 On-chip hardened I2C block

 Applications examples

 Dual MIPI CSI-2 to Single MIPI CSI-2 Aggregation

 Quad MIPI CSI-2 to Single MIPI CSI-2 Aggregation

 Single MIPI DSI to Single MIPI DSI Repeater

 Single MIPI CSI-2 to Single MIPI CSI-2 Repeater

 Single MIPI DSI to Dual MIPI DSI Splitter

 Single MIPI CSI-2 to Dual MIPI CSI-2 Splitter

 MIPI DSI to OpenLDI/FPD-Link/LVDS Translator

 OpenLDI/FPD-Link/LVDS to MIPI DSI Translator

 MIPI DSI/CSI-2 to CMOS Translator

 CMOS to MIPI DSI/CSI-2 Translator

 subLVDS to MIPI CSI-2 Translator

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