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Lattice CPLD ispLSI 1000 Family

CPLD ispLSI 1000 Family

The ispLSI is a High-Density Programmable Logic Device containing 384 Registers, 128 Universal I/O pins, five Dedicated Clock Input Pins, eight Output Routing Pools (ORP) and a Global Routing Pool (GRP) which allows complete inter-connectivity between all of these elements.

HIGH-DENSITY PROGRAMMABLE LOGIC 128 I/O Pins 11000 PLD Gates 384 Registers High Speed Global Interconnect Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc. Small Logic Block Size for Random Logic HIGH-PERFORMANCE E CMOS TECHNOLOGY fmax = 90 MHz Maximum Operating Frequency tpd 12 ns Propagation Delay TTL Compatible Inputs and Outputs Electrically Erasable and Reprogrammable Non-Volatile 100% Tested at Time of Manufacture Unused Product Term Shutdown Saves Power IN-SYSTEM PROGRAMMABLE 5V In-System Programmable (ISPTM) using Lattice ISP or Boundary Scan Test (IEEE 1149.1) Protocol Increased Manufacturing Yields, Reduced Time-toMarket, and Improved Product Quality Reprogram Soldered Devices for Faster Debugging 100% IEEE 1149.1 BOUNDARY SCAN COMPATIBLE OFFERS THE EASE OF USE AND FAST SYSTEM SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY OF FIELD PROGRAMMABLE GATE ARRAYS Complete Programmable Device Can Combine Glue Logic and Structured Designs Enhanced Pin Locking Capability Five Dedicated Clock Input Pins Synchronous and Asynchronous Clocks Programmable Output Slew Rate Control to Minimize Switching Noise Flexible Pin Placement Optimized Global Routing Pool Provides Global Interconnectivity ispDesignEXPERTTM ­ LOGIC COMPILER AND COMPLETE ISP DEVICE DESIGN SYSTEMS FROM HDL SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING Superior Quality of Results Tightly Integrated with Leading CAE Vendor Tools Productivity Enhancing Timing Analyzer, Explore Tools, Timing Simulator and ispANALYZERTM PC and UNIX Platforms

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