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Home > FPGA Familis > MAX 9000 EPLD > EPM9560ABC356-10

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$825.490 - $1361.931 | 1 Pieces(Min. Order)

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Factory Excess Stock / Franchised Distributor
Product Categories:
CPLD - Complex Programmable Logic Devices
CPLD MAX 9000 Family 12K Gates 560 Macro Cells 144.9MHz 5V 356-Pin BGA Tray
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EPM9560ABC356-10 FPGAs Overview

The MAX 9000 family of in-system-programmable, high-density, highperformance EPLDs is based on Altera’s third-generation MAX architecture. Fabricated on an advanced CMOS technology, the EEPROMbased MAX EPM9560ABC356-10 provides 6,000 to 12,000 usable gates, pin-to-pin delays as fast as 10 ns, and counter speeds of up to 144 MHz.

The INTEL CPLD - Complex Programmable Logic Devices series EPM9560ABC356-10 is MAX® 9000 Programmable Logic Device (PLD) Family; 356 pin BGA; 0 to 90°C, View Substitutes & Alternatives along with datasheets, stock, pricing from Authorized Distributors at, and you can also search for other FPGAs products.


■ High-performance CMOS EEPROM-based programmable logic
devices (PLDs) built on third-generation Multiple Array MatriX
(MAX) architecture
■ 5.0-V in-system programmability (ISP) through built-in IEEE Std.
1149.1 Joint Test Action Group (JTAG) interface
■ Built-in JTAG boundary-scan test (BST) circuitry compliant with IEEE
Std. 1149.1-1990
■ High-density erasable programmable logic device (EPLD) family
ranging from 6,000 to 12,000 usable gates (see Table 1)
■ 10-ns pin-to-pin logic delays with counter frequencies of up to
144 MHz
■ Fully compliant with the peripheral component interconnect Special
Interest Group’s (PCI SIG) PCI Local Bus Specification, Revision 2.2
■ Dual-output macrocell for independent use of combinatorial and
registered logic
■ FastTrack Interconnect for fast, predictable interconnect delays
■ Input/output registers with clear and clock enable on all I/O pins
■ Programmable output slew-rate control to reduce switching noise
■ MultiVolt I/O interface operation, allowing devices to interface with
3.3-V and 5.0-V devices
■ Configurable expander product-term distribution allowing up to 32
product terms per macrocell
■ Programmable power-saving mode for more than 50% power
reduction in each macrocell                                                


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  • Enter the "EPM9560ABC356-10" keyword in the search box of the website, or find these through the Download Channel or FPGA Forum .
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Application Field

  • AI

    Artificial Intelligence

  • 5G Technology

    5G Technology

  • Cloud Computing

    Cloud Computing

  • Consumer Electronics

    Consumer Electronics

  • Wireless

    Wireless Technology

  • Industrial Control

    Industrial Control

  • Internet of Things

    Internet of Things

  • Medical Equipment

    Medical Equipment

EPM9560ABC356-10 Specifications

Specification Value
Series MAX 9000
Memory Type EEPROM
Number of Macrocells 560
Maximum Operating Frequency 144 MHz
Delay Time 10 ns
Number of Programmable I/Os 216
Operating Supply Voltage 5 V
Maximum Operating Temperature + 70 C
Minimum Operating Temperature 0 C
Package / Case BGA-356
Mounting Style SMD/SMT
Packaging Tray
Supply Current 174 mA
Supply Voltage - Max 5.25 V
Supply Voltage - Min 4.75 V

Technical Documents

Circuit Diagram


EPM9560ABC356-10 PDF Preview

EPM9560ABC356-10 Tags

  • INTEL EPM9560A
  • EPM9560A development board
  • MAX 9000 Devices evaluation kit
  • INTEL MAX 9000 Devices development board
  • MAX 9000 Devices starter kit
  • MAX 9000 Devices EPM9560A
  • EPM9560A reference design
  • EPM9560A evaluation board
  • EPM9560ABC356-10 Datasheet PDF

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  • Intel Corporation
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    10+ $1167.3727
    25+ $1021.4482
    100+ $961.3664

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  • Intel Corporation
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  • 1+ $1,169.4400
    5+ $1,079.4800
    10+ $1,002.3800
    25+ $877.0800
    100+ $825.4900

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