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FPGAKey Technical Documents
Download DatasheetThe EPM7128STI100-10 of MAX 7000 family of high-density, high-performance PLDs is based on Altera’s second-generation MAX architecture. Fabricated with advanced CMOS technology, the EEPROM-based MAX 7000 family provides 600 to 5,000 usable gates, ISP, pin-to-pin delays as fast as 5 ns, and counter speeds of up to 175.4 MHz. EPM7128STI100-10 devices in the -5, -6, -7, and -10 speed grades as well as MAX 7000 and MAX 7000E devices in -5, -6, -7, -10P.
The INTEL Embedded - CPLDs (Complex Programmable Logic Devices) series EPM7128STI100-10 is CPLD MAX 7000S Family 2.5K Gates 128 Macro Cells 100MHz 5V 100-Pin TQFP Tray, View Substitutes & Alternatives along with datasheets, stock, pricing from Authorized Distributors at FPGAkey.com, and you can also search for other FPGAs products.■ 5.0-V in-system programmability (ISP) through the built-in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface available in MAX 7000S devices
– ISP circuitry compatible with IEEE Std. 1532
■ Includes 5.0-V MAX 7000 devices and 5.0-V ISP-based MAX 7000S devices
■ Built-in JTAG boundary-scan test (BST) circuitry in MAX7000S devices with 128 or more macrocells
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| Specification | Value |
|---|---|
| Series | MAX 7000 |
| Memory Type | EEPROM |
| Number of Macrocells | 128 |
| Maximum Operating Frequency | 192.3 MHz |
| Delay Time | 5 ns |
| Number of Programmable I/Os | 84 |
| Operating Supply Voltage | 3.3 V |
| Maximum Operating Temperature | + 85℃ |
| Minimum Operating Temperature | - 40℃ |
| Package / Case | TQFP-100 |
| Mounting Style | SMD/SMT |
| Packaging | Tray |
| Supply Voltage - Max | 3.6 V |
| Supply Voltage - Min | 3 V |
1+ $171.569
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25000+ $12.9300
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