$71.183 - $64.065 | 1 Pieces(Min. Order)
For product pricing customization or other inquiries
FPGAKey Technical Documents
Download DatasheetThe MAX 7000 family of high-density, high-performance PLDs is based on Altera’s second-generation MAX architecture. Fabricated with advanced CMOS technology, the EEPROM-based MAX EPM7128EQI100-15 provides 600 to 5,000 usable gates, ISP, pin-to-pin delays as fast as 5 ns, and counter speeds of up to 175.4 MHz. MAX 7000S devices in the -5, -6, -7, and -10 speed grades as well as MAX 7000 and MAX 7000E devices in -5, -6, -7, -10P, and -12P speed grades comply with the PCI Special Interest.
The INTEL CPLD - Complex Programmable Logic Devices series EPM7128EQI100-15 is CPLD MAX 7000 Family 2.5K Gates 128 Macro Cells 76.9MHz 5V 100-Pin PQFP Tray, View Substitutes & Alternatives along with datasheets, stock, pricing from Authorized Distributors at FPGAkey.com, and you can also search for other FPGAs products.■ 5.0-V in-system programmability (ISP) through the built-in IEEE Std. 1149.1
Joint Test Action Group (JTAG) interface available in MAX 7000S devices
– ISP circuitry compatible with IEEE Std. 1532
■ Includes 5.0-V MAX 7000 devices and 5.0-V ISP-based MAX 7000S devices
■ Built-in JTAG boundary-scan test (BST) circuitry in MAX7000S devices with 128 or more macrocells
Artificial Intelligence
5G Technology
Cloud Computing
Consumer Electronics
Wireless Technology
Industrial Control
Internet of Things
Medical Equipment
| Specification | Value |
|---|---|
| Series | MAX 7000 |
| Memory Type | EEPROM |
| Number of Macrocells | 128 |
| Maximum Operating Frequency | 125 MHz |
| Delay Time | 7.5 ns |
| Number of Programmable I/Os | 84 |
| Operating Supply Voltage | 5 V |
| Maximum Operating Temperature | + 85℃ |
| Minimum Operating Temperature | - 40℃ |
| Package / Case | PQFP-100 |
| Mounting Style | SMD/SMT |
| Packaging | Tube |
| Supply Voltage - Max | 5.25 V |
| Supply Voltage - Min | 4.75 V |
1+ $71.1825
Support