$11.735 - $29.412 | 1 Pieces(Min. Order)
For product pricing customization or other inquiries
FPGAKey Technical Documents
Download DatasheetDescription:
The MAX 7000 family of high-density, high-performance PLDs is based on Altera’s second-generation MAX architecture. Fabricated with advanced CMOS technology, the EEPROM-based MAX 7000 family provides 600 to 5,000 usable gates, ISP, pin-to-pin delays as fast as 5 ns, and counter speeds of up to 175.4 MHz. MAX 7000S devices in the -5, -6, -7, and -10 speed grades as well as MAX 7000 and MAX 7000E devices in -5, -6, -7, -10P, and -12P speed grades comply with the PCI Special Interest Group (PCI SIG).
Features:
■ High-performance, EEPROM-based programmable logic devices
(PLDs) based on second-generation MAX architecture
■ 5.0-V in-system programmability (ISP) through the built-in IEEE Std.1149.1 Joint Test Action Group(JTAG) interface available in MAX 7000S devices
ISP circuitry compatible with IEEE Std.1532
Includes 5.0-V MAX 7000 devices and 5.0-VISP-based MAX 7000S devices
■ Built-in JTAG boundary-scan test (BST) circuitry in MAX 7000S devices with 128 or more macrocells
■ Complete EPLD family with logic densities ranging from 600 to
5,000 usable gates(see Tables 1 and 2)
■ 5-ns pin-to-pin logic delays with up to 175.4-MHz counter frequencies(including interconnect)
■ PCI-compliant devices available
■ Open-drain output option in MAX 7000S devices Programmable macrocell flipflops with individual clear,preset,clock,and clock enable controls a Programmable power-saving mode for a reduction of over 50%in each macrocel1
■ Configurable expander product-term distribution,allowing up to
32 product terms per macrocell
■ 44 to 208 pins available in plastic J-lead chip carrier(PLCC),ceramic pin-grid array(PGA),plastic quad flat pack(PQFP),power quad flat pack(RQFP),and 1.0-mm thin quad flat pack(TQFP)packages
■ Programmable security bit for protection of proprietary designs
■ 3.3-V or 5.0-V operation
MultiVoltM I/O interface operation,allowing devices to interface with 3.3-V or 5.0-V devices(MultiVolt I/O operation is not available in 44-pin packages)
Pin compatible with low-voltage MAX 7000A and MAX 7000B devices
■ Enhanced features available in MAX 7000E and MAX 7000S devices
Six pin-or logic-driven output enable signals
Two global clock signals with optional inversion Enhanced interconnect resources for improved routability Fast input setup times provided by a dedicated path from I/O pin to macrocell registers
Programmable output slew-rate control
■ Software design support and automatic place-and-route provided by Altera's development system for Windows-based PCs and Sun SPARCstation,and HP 9000 Series 700/800 workstations
■ 5.0-V in-system programmability (ISP) through the built-in IEEE Std. 1149.1
Joint Test Action Group (JTAG) interface available in MAX 7000S devices
– ISP circuitry compatible with IEEE Std. 1532
■ Includes 5.0-V MAX 7000 devices and 5.0-V ISP-based MAX 7000S devices
■ Built-in JTAG boundary-scan test (BST) circuitry in MAX7000S devices with 128 or more macrocells
Artificial Intelligence
5G Technology
Cloud Computing
Consumer Electronics
Wireless Technology
Industrial Control
Internet of Things
Medical Equipment
| Specification | Value |
|---|---|
| Series | MAX 7000 |
| Memory Type | EEPROM |
| Number of Macrocells | 128 |
| Maximum Operating Frequency | 125 MHz |
| Delay Time | 7.5 ns |
| Number of Programmable I/Os | 68 |
| Operating Supply Voltage | 5 V |
| Maximum Operating Temperature | + 70 C |
| Minimum Operating Temperature | 0 C |
| Package / Case | PLCC-84 |
| Mounting Style | SMD/SMT |
| Packaging | Tube |
| Supply Voltage - Max | 5.25 V |
| Supply Voltage - Min | 4.75 V |
5+ $40.4100
Support