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Home > FPGA Familis > MAX 7000 CPLD > EPM7064STC44-10N

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$7.500 - $14.706 | 1 Pieces(Min. Order)




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Embedded - CPLDs (Complex Programmable Logic Devices)

CPLD MAX 7000S Family 1.25K Gates 64 Macro Cells 100MHz 5V 44-Pin TQFP Tray

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EPM7064STC44-10N FPGAs Overview


■ High-performance, EEPROM-based programmable logic devices (PLDs) based on second-generation MAX® architecture
■ 5.0-V in-system programmability (ISP) through the built-in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface available in
MAX 7000S devices– ISP circuitry compatible with IEEE Std. 1532
■ Includes 5.0-V MAX 7000 devices and 5.0-V ISP-based MAX 7000S devices
■ Built-in JTAG boundary-scan test (BST) circuitry in MAX7000S devices with 128 or more macrocells
■ Complete EPLD family with logic densities ranging from 600 to 5,000 usable gates (see Tables 1 and 2) ■ 5-ns pin-to-pin logic delays with up to 175.4-MHz counter frequencies (including interconnect)
■ PCI-compliant devices available


■ Open-drain output option in MAX 7000S devices
■ Programmable macrocell flipflops with individual clear, preset, clock, and clock enable controls
■ Programmable power-saving mode for a reduction of over 50% in each macrocell
■ Configurable expander product-term distribution, allowing up to 32 product terms per macrocell
■ 44 to 208 pins available in plastic J-lead chip carrier (PLCC), ceramic pin-grid array (PGA), plastic quad flat pack (PQFP), power quad flat pack (RQFP), and 1.0-mm thin quad flat pack (TQFP) packages
■ Programmable security bit for protection of proprietary designs
■ 3.3-V or 5.0-V operation– MultiVoltTM I/O interface operation, allowing devices to interface with 3.3-V or 5.0-V devices (MultiVolt I/O operation is not available in 44-pin packages)– Pin compatible with low-voltage MAX 7000A and MAX 7000B
■ Enhanced features available in MAX 7000E and MAX 7000S devices

– Six pin- or logic-driven output enable signals
– Two global clock signals with optional inversion
– Enhanced interconnect resources for improved routability
– Fast input setup times provided by a dedicated path from I/O pin to macrocell registers
– Programmable output slew-rate control
■ Software design support and automatic place-and-route provided by Altera’s development system for Windows-based PCs and Sun SPARCstation, and HP 9000 Series 700/800 workstations

General Description

■ Additional design entry and simulation support provided by EDIF 2 0 0 and 3 0 0 netlist files, library of parameterized modules (LPM), Verilog HDL, VHDL, and other interfaces to popular EDA tools from
manufacturers such as Cadence, Exemplar Logic, Mentor Graphics, OrCAD, Synopsys, and VeriBest
■ Programming support
– Altera’s Master Programming Unit (MPU) and programming hardware from third-party manufacturers program all MAX 7000 devices

The MAX 7000 family of high-density, high-performance PLDs is based on Altera’s second-generation MAX architecture. Fabricated with

advanced CMOS technology, the EEPROM-based MAX 7000 family provides 600 to 5,000 usable gates, ISP, pin-to-pin delays as fast as 5 ns,and counter speeds of up to 175.4 MHz. MAX 7000S devices in the -5, -6,-7, and -10 speed grades as well as MAX 7000 and MAX 7000E devices in-5, -6, -7, -10P, and -12P speed grades comply with the PCI Special Interest Group (PCI SIG) PCI Local Bus Specification, Revision 2.2. See Table 3 for available speed grades.– The BitBlasterTM serial download cable, ByteBlasterMVTM parallel port download cable, and MasterBlasterTM serial/universal serial bus (USB) download cable program MAX7000S devices

The INTEL Embedded - CPLDs (Complex Programmable Logic Devices) series EPM7064STC44-10N is CPLD MAX 7000S Family 1.25K Gates 64 Macro Cells 100MHz 5V 44-Pin TQFP Tray, View Substitutes & Alternatives along with datasheets, stock, pricing from Authorized Distributors at, and you can also search for other FPGAs products.


  • Built-in JTAG boundary-scan test
  • PCI-compliant devices available
  • 5ns pin-to-pin logic delays with up to 175.4MHz counter frequencies
  • Open-drain output option
  • Programmable macrocell flip-flops with individual clear, preset, clock and clock enable controls
  • Programmable power-saving mode for a reduction of over 50% in each macrocell
  • Six pin or logic-driven output enable signals
  • Two global clock signals with optional inversion
  • Enhanced interconnect resources for improved routability
  • Programmable output slew-rate control


  • Q: Does the price of EPM7064STC44-10N devices fluctuate frequently?
  • The FPGAkey search engine monitors the EPM7064STC44-10N inventory quantity and price of global electronic component suppliers in real time, and regularly records historical price data. You can view the historical price trends of electronic components to provide a basis for your purchasing decisions.
  • Q: Do I have to sign up on the website to make an inquiry for EPM7064STC44-10N?
  • No, only submit the quantity, email address and other contact information required for the inquiry of EPM7064STC44-10N, but you need to sign up for the post comments and resource downloads.
  • Q: How can I obtain software development tools related to the INTEL FPGA platform?
  • Quartus Prime Modelsim is the corresponding programming software for FPGA produced by Altera/Intel. The specific choice depends on personal habits and functional requirements to specifically select a more suitable match. You can search and download through the FPGA resource channel.
  • Q: Where can I purchase INTEL EPM7064S Development Boards, Evaluation Boards, or MAX 7000 CPLD Starter Kit? also provide technical information?
  • FPGAkey does not provide development board purchase services for the time being, but customers often consult about ZedBoard, Basys 3 board, TinyFPGA BX, Nexys4-DDR, Terasic DE10-Nano, Digilent Arty S7, etc. If you need relevant technical information, you can submit feedback information, our technicians will contact you soon.
  • Q: How to obtain EPM7064STC44-10N technical support documents?
  • Enter the "EPM7064STC44-10N" keyword in the search box of the website, or find these through the Download Channel or FPGA Forum .
  • Q: What should I do if I did not receive the technical support for EPM7064STC4410N in time?
  • Depending on the time difference between your location and our location, it may take several hours for us to reply, please be patient, our FPGA technical engineer will help you with the EPM7064STC44-10N pinout information, replacement, datasheet in pdf, programming tools, starter kit, etc.

Application Field

  • AI

    Artificial Intelligence

  • 5G Technology

    5G Technology

  • Cloud Computing

    Cloud Computing

  • Consumer Electronics

    Consumer Electronics

  • Wireless

    Wireless Technology

  • Industrial Control

    Industrial Control

  • Internet of Things

    Internet of Things

  • Medical Equipment

    Medical Equipment

Technical Attributes

  • Series

    MAX 7000

  • Memory Type


  • Number of Macrocells


  • Maximum Operating Frequency

    222.2 MHz

  • Delay Time

    4.5 ns

  • Number of Programmable I/Os


  • Operating Supply Voltage

    3.3 V

  • Maximum Operating Temperature

    + 70 C

  • Minimum Operating Temperature

    0 C

  • Package / Case


  • Mounting Style


  • Packaging


  • Supply Voltage - Max

    3.6 V

  • Supply Voltage - Min

    3 V

Technical Documents

Circuit Diagram


EPM7064STC44-10N PDF Preview

EPM7064STC44-10N Tags

  • INTEL EPM7064S
  • EPM7064S development board
  • MAX 7000 evaluation kit
  • INTEL MAX 7000 development board
  • MAX 7000 starter kit
  • MAX 7000 EPM7064S
  • EPM7064S reference design
  • EPM7064S evaluation board
  • EPM7064STC44-10N Datasheet PDF

Other Authorized Distributors (Fpgakey will provide Competitive price from all franchised resource.)

  • BUY
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  • EPM7064STC44-10N
  • Intel Corporation
  • 41375
  • 1+ $58.0903
    25+ $39.9342
    100+ $31.9566
    500+ $26.6228
    1000+ $18.2609
    2500+ $16.8168
    5000+ $15.9783
    10000+ $15.7803
    25000+ $15.594

  • mouser
  • EPM7064STC44-10N
  • Altera Corporation
  • CPLD - Complex Programmable Logic Devices CPLD - MAX 7000 64 Macro 36 IOs
  • 1334
  • 1+ $7.50

  • verical
  • EPM7064STC44-10N
  • CPLD MAX® 7000S Family 1.25K Gates 64 Macro Cells 100MHz 5V 44-Pin TQFP Tray
  • 0
  • 2+ $49.8800
    25+ $34.2900
    100+ $27.4400
    500+ $22.8600
    1000+ $15.6800
    2500+ $14.4400
    5000+ $13.7200
    10000+ $13.5500
    25000+ $13.3900

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