The MAX 7000 family of high-density, high-performance PLDs is based on Altera’s second-generation MAX architecture. Fabricated with advanced CMOS technology, the EEPROM-based MAX 7000 family provides 600 to 5,000 usable gates, ISP, pin-to-pin delays as fast as 5 ns, and counter speeds of up to 175.4 MHz. MAX 7000S devices in the -5, -6, -7, and -10 speed grades.
In-system programmable MAX 7000S devices—include the EPM7032S, EPM7064S, EPM7128S, EPM7160S, EPM7192S, and EPM7256S devices. EPM7064STC100-10N devices have the enhanced features of MAX 7000E devices as well as JTAG BST circuitry in devices with 128 or more macrocells, ISP, and an open-drain output option.
The EPM7064STC100-10N architecture supports 100% TTL emulation and high-density integration of SSI, MSI, and LSI logic functions. The EPM7064STC100-10N architecture easily integrates multiple devices ranging from PALs, GALs, and 22V10s to MACH and pLSI devices. EPM7064STC100-10N devices are available in a wide range of packages, including PLCC, PGA, PQFP, RQFP, and TQFP packages.The INTEL Embedded - CPLDs (Complex Programmable Logic Devices) series EPM7064STC100-10N is CPLD MAX 7000S Family 1.25K Gates 64 Macro Cells 100MHz 5V 100-Pin TQFP Tray, View Substitutes & Alternatives along with datasheets, stock, pricing from Authorized Distributors at FPGAkey.com, and you can also search for other FPGAs products.
■ 5.0-V in-system programmability (ISP) through the built-in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface available in MAX 7000S devices
– ISP circuitry compatible with IEEE Std. 1532
■ Includes 5.0-V MAX 7000 devices and 5.0-V ISP-based MAX 7000S devices
■ 5-ns pin-to-pin logic delays with up to 175.4-MHz counter frequencies (including interconnect)
■ Built-in JTAG boundary-scan test (BST) circuitry in MAX7000S devices with 128 or more macrocells
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