$30.119 - $27.107 | 1 Pieces(Min. Order)
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CPLD - Complex Programmable Logic Devices
CPLD MAX 7000 Family 1.25K Gates 64 Macro Cells 76.9MHz 5V 100-Pin PQFP Tray
The EPM7064QI100-15 of high-density, high-performance PLDs is based on Altera’s second-generation MAX architecture. Fabricated with advanced CMOS technology, the EEPROM-based MAX 7000 family provides 600 to 5,000 usable gates, ISP, pin-to-pin delays as fast as 5 ns, and counter speeds of up to 175.4 MHz.
The Altera's EPM7064QI100-15 devices in the -5, -6, -7, and -10 speed grades as well as MAX 7000 and MAX 7000E devices in -5, -6, -7, -10P, and -12P speed grades comply with the PCI Special Interest Group (PCI SIG) PCI Local Bus Specification, Revision 2.2.
In-system programmable EPM7064QI100-15 devices—called MAX 7000S devices—include the EPM7032S, EPM7064S, EPM7128S, EPM7160S, EPM7192S, and EPM7256S devices. MAX 7000S devices have the enhanced features of EPM7064QI100-15 devices as well as JTAG BST circuitry in devices with 128 or more macrocells, ISP, and an open-drain output option.The INTEL CPLD - Complex Programmable Logic Devices series EPM7064QI100-15 is MAX® 7000 Programmable Logic Device Family; 100 pin PQFP; -40 to 105°C, View Substitutes & Alternatives along with datasheets, stock, pricing from Authorized Distributors at FPGAkey.com, and you can also search for other FPGAs products.
■ 5.0-V in-system programmability (ISP) through the built-in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface available in MAX 7000S devices
– ISP circuitry compatible with IEEE Std. 1532
■ Includes 5.0-V MAX 7000 devices and 5.0-V ISP-based MAX 7000S devices
■ Built-in JTAG boundary-scan test (BST) circuitry in EPM7064 devices with 128 or more macrocells
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