$7.857 - $28.676 | 1 Pieces(Min. Order)
INTEL
TQFP-44
No RoHS
Active
Factory Excess Stock / Franchised Distributor
Embedded - CPLDs (Complex Programmable Logic Devices)
CPLD MAX 7000A Family 1.25K Gates 64 Macro Cells 100MHz 3.3V 44-Pin TQFP Tray
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FPGAKey Technical Documents
Download DatasheetMAX 7000A (including MAX 7000AE) devices are high-density, highperformance devices based on Altera’s second-generation MAX architecture. Fabricated with advanced CMOS technology, the EEPROM based EPM7064AETC44-10 devices operate with a 3.3-V supply voltage and provide 600 to 10,000 usable gates, ISP, pin-to-pin delays as fast as 4.5 ns, and counter speeds of up to 227.3 MHz. EPM7064AETC44-10 devices in the -4, -5, -6, -7, and some -10 speed grades are compatible with the timing.
The EPM7064AETC44-10 architecture includes four dedicated inputs that can be used as general-purpose inputs or as high-speed, global control signals (clock, clear, and two output enable signals) for each macrocell and I/O pin .
The INTEL Embedded - CPLDs (Complex Programmable Logic Devices) series EPM7064AETC44-10 is CPLD MAX 7000A Family 1.25K Gates 64 Macro Cells 100MHz 3.3V, View Substitutes & Alternatives along with datasheets, stock, pricing from Authorized Distributors at FPGAkey.com, and you can also search for other FPGAs products.■ High-performance 3.3-V EEPROM-based programmable logic devices (PLDs) built on second-generation Multiple Array MatriX (MAX) architecture (see Table 1)
■ 3.3-V in-system programmability (ISP) through the built-in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface with advanced pin-locking capability
– MAX 7000AE device in-system programmability (ISP) circuitry compliant with IEEE Std. 1532
– EPM7128A and EPM7256A device ISP circuitry compatible with IEEE Std. 1532
■ Built-in boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1
■ Supports JEDEC Jam Standard Test and Programming Language (STAPL) JESD-71
■ Enhanced ISP features – Enhanced ISP algorithm for faster programming (excluding EPM7128A and EPM7256A devices)
■ Additional design entry and simulation support provided by EDIF 2 0 0 and 3 0 0 netlist files, library of parameterized modules (LPM), Verilog HDL, VHDL, and other interfaces to popular EDA tools from manufacturers such as Cadence, Exemplar Logic, Mentor Graphics, OrCAD, Synopsys, and VeriBest
– ISP_Done bit to ensure complete programming (excluding EPM7128A and EPM7256A devices)
– Pull-up resistor on I/O pins during in-system programming
■ Pin-compatible with the popular 5.0-V MAX 7000S devices
■ High-density PLDs ranging from 600 to 10,000 usable gates
■ Extended temperature range
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Series
MAX 7000
Memory Type
EEPROM
Number of Macrocells
64
Maximum Operating Frequency
222.2 MHz
Delay Time
4.5 ns
Number of Programmable I/Os
36
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Package / Case
TQFP-44
Mounting Style
SMD/SMT
Packaging
Tray
Supply Voltage - Max
3.6 V
Supply Voltage - Min
3 V
1+ $10.1351
1+ $10.1351
1+ $8.7400
160+ $80.7751
160+ $80.7751
160+ $80.7751
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