$15.500 - $110.294 | 1 Pieces(Min. Order)
INTEL
PDIP-8
Obsolete
Factory Excess Stock / Franchised Distributor
Memory - Configuration Proms for FPGA's
EPC SRAM Chip Sync 3.3V/5V 1M-bit 8-Pin PDIP Tube
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FPGAKey Technical Documents
Download DatasheetThe MAX 9000 EPC1PI8N of in-system-programmable, high-density, highperformance EPLDs is based on Altera’s third-generation MAX architecture. Fabricated on an advanced CMOS technology, the EEPROMbased MAX 9000 family EPC1PI8N provides 6,000 to 12,000 usable gates, pin-to-pin delays as fast as 10 ns, and counter speeds of up to 144 MHz.
High-performance CMOS EEPROM-based programmable logic devices (PLDs) built on third-generation Multiple Array MatriX (MAX) architecture.
The INTEL Memory - Configuration Proms for FPGA's series EPC1PI8N is FPGA Configuration Memory, SRAM, 1 Mbit, 8 MHz, JTAG, Serial, DIP, 8 Pins, View Substitutes & Alternatives along with datasheets, stock, pricing from Authorized Distributors at FPGAkey.com, and you can also search for other FPGAs products.High-performance CMOS EEPROM-based programmable logic devices (PLDs) built on
third-generation Multiple Array MatriX (MAX) architecture
■ 5.0-V in-system programmability (ISP) through built-in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface
■ Built-in JTAG boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1-1990
■ High-density erasable programmable logic device (EPLD) family ranging from 6,000 to 12,000 usable gates (see Table 1)
■ 10-ns pin-to-pin logic delays with counter frequencies of up to 144 MHz
■ Fully compliant with the peripheral component interconnect Special Interest Group’s (PCI SIG) PCI Local Bus Specification, Revision 2.2
■ Dual-output macrocell for independent use of combinatorial and registered logic
■ FastTrack Interconnect for fast, predictable interconnect delays
■ Input/output registers with clear and clock enable on all I/O pins
■ Programmable output slew-rate control to reduce switching noise
■ MultiVolt I/O interface operation, allowing devices to interface with 3.3-V and 5.0-V devices
■ Configurable expander product-term distribution allowing up to 32 product terms per macrocell
■ Programmable power-saving mode for more than 50% power reduction in each macrocell
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Memory Type
Flash
Memory Size
1 Mbit
Operating Frequency
8 MHz
Supply Voltage - Max
5.25 V
Supply Voltage - Min
3 V
Supply Current
50 uA
Maximum Operating Temperature
+ 85℃
Minimum Operating Temperature
- 40℃
Mounting Style
Through Hole
Package / Case
PDIP-8
Packaging
Tube
Series
EPC1
1+ $15.50
1+ $15.50
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