Assign an array to another array.
Posted by Ficken Bumsen · On Aug 03, 2020 at 09:54 AM
2
Assign an array to another array.
Posted by Ficken Bumsen · On Aug 03, 2020 at 09:54 AM
2
VHDL design example: pseudo-random number generator.
Posted by Michael Pinneke · On Jul 07, 2020 at 19:40 PM
1
VHDL design example: Stepper motor controller programming.
Posted by Juan Hsiung · On Jul 07, 2020 at 19:37 PM
1
The connection between ddr2 and virtex 5.
Posted by stephen david · On Jul 07, 2020 at 13:50 PM
3
The problem of assignment in the state machine.
Posted by Meg Peng · On Jul 07, 2020 at 13:45 PM
1
JTAG cannot detect the PROM device.
Posted by jamie · On Jul 07, 2020 at 12:30 PM
2
Anxious, what is the core of prawn PLBv46 Bridge for PCI Express used for?
Posted by sonia touati · On Jul 07, 2020 at 12:27 PM
2
Posted by Mark Arvin · On Jul 07, 2020 at 12:21 PM
1
Posted by Rodolfo Lehner · On Jul 07, 2020 at 12:14 PM
3
The timing problem of mch_emc IP.
Posted by Michael Pinneke · On Jul 07, 2020 at 12:00 PM
0
Which xilinx chip is the strongest under RMB 100?
Posted by Stefan Andrey · On Jul 07, 2020 at 11:55 AM
3
RockIO core configuration issue.
Posted by sonia touati · On Jul 07, 2020 at 11:51 AM
2
Dynamically programmable DRU for high-speed serial I/O.
Posted by Mark Arvin · On Jul 07, 2020 at 11:49 AM
0
How to achieve 10M to 100M frequency doubling
Posted by DORIS · On Jul 07, 2020 at 11:33 AM
4
I use V5 fiber to receive high bit error, please beg for advice! ! !
Posted by Michael Pinneke · On Jul 07, 2020 at 11:29 AM
1
V5 chip is too hot, can only add a fan?
Posted by Michael Pinneke · On Jul 07, 2020 at 11:26 AM
3
How to solve various unsatisfactory clock constraints.
Posted by tomasz pindar · On Jul 07, 2020 at 11:19 AM
4
Has anyone done Gigabit Ethernet for V5.
Posted by Philipp Zielinski · On Jul 07, 2020 at 11:14 AM
3
Consult the master RocketIO GTP physical implementation problem.
Posted by Juan Hsiung · On Jul 07, 2020 at 11:11 AM
2
Is there an FPGA board that can directly support floating point arithmetic?
Posted by Stefan Andrey · On Jul 07, 2020 at 11:09 AM
2
FPGA Spartan-3E Family 500K Gates 10476 Cells 657MHz 90nm Technology 1.2V 132-Pin CSBGA
Xilinx BGA56
FPGA Spartan-XL Family 5K Gates 238 Cells 217MHz 3.3V 100-Pin VTQFP
Xilinx QFP44
CPLD CoolRunner -II Family 750 Gates 32 Macro Cells 323MHz 0.18um, CMOS Technology 1.8V 44-Pin PLCC
Support
