Quartus II 11.0 cannot recognize USB Blaster.
Posted by Sylvia · On Nov 17, 2020 at 05:48 AM
5
Quartus II 11.0 cannot recognize USB Blaster.
Posted by Sylvia · On Nov 17, 2020 at 05:48 AM
5
There was a problem installing DSPBuilder 15.0.
Posted by Natasha Tokatlian · On Aug 17, 2020 at 19:00 PM
1
After the xilinx XC6SLX150 SPI flash is downloaded, the done is not raised.
Posted by Natasha Tokatlian · On Jul 06, 2020 at 14:03 PM
3
Error: Current license file does not support solution.
Posted by Mark Arvin · On Jul 06, 2020 at 13:59 PM
1
Can the pins of the nios II processor be reused?
Posted by Sylvia · On Jul 06, 2020 at 13:56 PM
2
Does quartus13 use vmf file simulation under this version?
Posted by Meg Peng · On Jul 06, 2020 at 13:54 PM
3
Posted by Jim.T · On Jul 06, 2020 at 13:51 PM
1
How to generate differential clock output?
Posted by Rodolfo Lehner · On Jul 06, 2020 at 13:43 PM
4
SPARTAN6 FPGA SPI mode download trouble, please give pointers.
Posted by Meg Peng · On Jul 06, 2020 at 12:28 PM
3
The program can be debugged by JTAG and cannot be downloaded to Flash. Guiqiu expert guidance.
Posted by Natasha Tokatlian · On Jul 06, 2020 at 12:25 PM
3
Can the warning compiled by quartus ii be ignored?
Posted by Mark Arvin · On Jul 06, 2020 at 12:22 PM
3
Ask: Who has used ODDR2 of xilinx?
Posted by Matteo Scalcione · On Jul 06, 2020 at 12:19 PM
3
The emulation that comes with Quaartus II 13 cannot be started.
Posted by Allen Chi · On Jul 06, 2020 at 12:12 PM
1
The ISE wiring constraint problem is very strange...
Posted by Jim.T · On Jul 06, 2020 at 12:09 PM
1
Posted by Natasha Tokatlian · On Jul 06, 2020 at 12:06 PM
2
Posted by Allen Chi · On Jul 06, 2020 at 11:59 AM
2
How to program nios program without source project? ? ?
Posted by Juan Hsiung · On Jul 06, 2020 at 11:51 AM
3
How to add off-chip SRAM module in Qsys?
Posted by Ficken Bumsen · On Jul 06, 2020 at 11:49 AM
2
Novice questions eagerly ask the great god to answer.
Posted by Ficken Bumsen · On Jul 06, 2020 at 11:46 AM
2
How to deal with the difference between quartus RTL simulation and gate simulation results.
Posted by Matteo Scalcione · On Jul 06, 2020 at 11:43 AM
3
Xilinx QFP100
Xilinx TQFP44
FPGA Spartan-XL Family 5K Gates 238 Cells 217MHz 3.3V 84-Pin PLCC
FPGA Spartan Family 10K Gates 466 Cells 166MHz 5V 144-Pin TQFP EP
CPLD CoolRunner -II Family 750 Gates 32 Macro Cells 323MHz 0.18um, CMOS Technology 1.8V 44-Pin PLCC
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