How to realize FPGA synthesis of SoC verification platform?

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  Oscar Posted on 2020/12/25 10:30:41

  This article uses the 32-bit microprocessor AEMB released by the OpenCores organization as the control center of the SoC system, and integrates the relevant IP cores released and maintained by the OpenCores organization on the target SoC system through the Wishbone bus interconnection specification, forming the final SoC verification platform.

  1 Introduction to AEMB and Wishbone bus
  

  AEMB is a high-efficiency open source microprocessor soft core, which is compatible with the Microblaze microprocessor developed by Xilinx for its devices in terms of instructions, and has an enhanced structure. It mainly has the following characteristics:
  

  ①The soft core is designed to be very small. Compared with some other microprocessor soft cores, it takes up less hardware logic resources in physical implementation;

  ②Support multi-threading on hardware, which can effectively execute operating system-related code;

  ③AEMB is developed under LGPL3, so it can be embedded into a large design as a part, and it is very suitable for some research institutes and universities or individuals to learn;

  ④Support Wishbone bus specification, can easily integrate some other open source IP cores that support Wishbone bus specification;

  ⑤The configurable functions of the system are defined completely through some parameters, such as the address space of the system and some other optional functional units;

  ⑥ 99% of the instructions are compatible with EDK6.2, and the already mature development tool chain can be easily used.

  The Wishbone bus specification is a system-on-chip IP core interconnection architecture. It defines a common logical interface between IP cores, reduces the difficulty of system component integration, improves the reusability, reliability and portability of system components, and accelerates the speed of product marketization. The Wishbone bus specification can be used for soft cores, solid cores and hard cores. It has no special requirements for development tools and target hardware, and is almost compatible with all existing comprehensive tools, and can be implemented with multiple hardware description languages. Wishbone bus provides 4 different IP core interconnection methods:

  1. Point-to-point, used for direct interconnection of two IP cores;

  2. Data flow, used for concurrent data transmission between multiple serial IP cores;

  3. Shared bus, multiple IP cores share a bus;

  4. Crossbar switch, which connects multiple master and slave components at the same time, can improve system throughput.

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  Duke Posted on 2020/12/25 21:34:38

  2 Overall framework of SoC system verification platform

  The main IP modules included in the SoC system are: 32-bit open source microprocessor soft core AEMB, interrupt controller, clock timer, Wishbone bus, on-chip RAM controller, SDRAM controller, SSRAM controller, Flash controller, UART16550 control GPIO controller. The overall structure of the entire SoC system is shown in Figure 1.

  In order to facilitate subsequent development and application, the Wishbone bus arbitration in this SoC system uses the open source IP soft core wb_conmax. It has an 8×16 structure, that is, 8 master devices and 16 slave devices can be used in the Wishbone bus module. Eight slave device interfaces and two master device interfaces are used in this system. The AEMB soft core does not provide a clock timer and interrupt controller. In order to use the soft core normally, an interrupt controller and a clock timer are added to the system. These two controllers are added as slave devices. For some applications that require little storage space, the system uses on-chip RAM as the main memory. However, the space of the FPGA on-chip memory is very limited. In order to be able to run an operating system that requires a large amount of storage space and to enable the system to power up normally, an external memory is required as the main memory of the system. Therefore, SDRAM, SSRAM controller and Flash memory are also added to the system. UART16550 controller and GPIO controller are connected in the system as two slave devices.

  3 Specific construction of SoC system verification platform

  3.1 Selection and configuration of AEMB version

  AEMB soft core uses the latest EDK62 version. The purpose of this design is the construction of the entire SoC system verification platform, and there is no requirement for the microprocessor performance and the specific application performance of the entire SoC system. In order to simplify the design, some optimization options that can be configured in the AEMB soft core are all disabled. This not only saves the occupation of FPGA hardware logic resources, but also avoids many problems caused by improper use of some specific details.

  3.2 Generation of on-chip RAM

  In order to reduce the occupation of FPGA logic resources and at the same time meet the storage and operation of the most basic startup code, the size of the on-chip memory is set to 4 KB. Use the MegaWizard Plug-In Manager tool in Altera's FPGA development environment QuartusII 9.0 to generate on-chip RAM with a set size of 4 KB. The on-chip storage file generated by the EDA development tool is only an HDL description file with relevant memory addresses, data and read and write control signals. In order to be able to be used in this SoC system, it needs to be packaged into a slave device that conforms to the Wishbone bus interface to be connected to the system's Wishbone bus.

  3.3 Configuration of off-chip storage controller

  In this SoC system, the off-chip memory controller mainly includes SDRAM, Flash, and SSRAM controllers. According to the needs of the actual memory chip on the DE2-70 development board of Taiwan Friends of the Crystal Company, the data bus width and address bus width of the controller are modified and customized accordingly. Under normal circumstances, SDRAM is used as the main memory of the system, and Flash is used to store some curing programs of the system. In the process of measuring time parameters of some real-time systems, in order to reduce the influence of the instability of the sequence in the program running space, the test programs are generally run in SSRAM devices.

  As the physical chip of the storage device, the ports of the data bus are basically bidirectional, while the data ports in the on-chip system are basically unidirectional. These off-chip storage controllers need to process the corresponding data ports when making physical board-level connections. Take the Flash controller as an example, the two-way I/O port of the data bus specifically realizes the RTL code as follows:

  

  The realization of the data bus bidirectional I/O of other memories (such as SDRAM, SSRAM) is also accomplished by this method.

  3.4 Interrupt controller and clock timer configuration

  The interrupt controller is mainly used to receive an interrupt request from an external interrupt source, and then send an interrupt request to the CPU after processing the interrupt request, waiting for the CPU to respond to the interrupt and process it. In the process of the CPU responding to the interrupt, the interrupt controller is still responsible for managing the interrupt request of the external interrupt source, so as to realize the nesting and prohibition of interrupts. In this design, the logic structure of the interrupt controller is shown in Figure 2. The used interrupt controller is mainly responsible for receiving interrupt requests from the on-chip IP core and off-chip devices, and then sends the interrupt to the microprocessor according to certain priority and rules. The microprocessor can manage and view the interrupt priority and interrupt status by setting and reading the corresponding interrupt register.

  The clock timer is mainly used as the clock tick timer of the operating system, and is essentially a simple counter. The counter will automatically increase by 1 every time the system clock comes, and a clock interrupt will be generated when the counter value reaches the set value. PTC is a pulse timing counter that supports Wishbone bus interface released by OpenCores organization. It can not only be used as a clock timer, but also can generate PWM pulse output by setting the configuration register. The PTC timer function is mainly used in this SoC system.

  3.5 Allocation of address space

  According to the characteristics of the devices on the DE2-70 development board, the interrupt exception vector table of the AEMB microprocessor and the logical realization of wb_conmax, the system address space allocation result is:

  

  4 FPGA synthesis realization of SoC system

  For the DE2-70 development board, the CycloneII series device EP2C70F896C6 is selected when performing the FPGA synthesis of the SoC system. The system clock frequency is preset to 50 MHz, and synthesis is performed without additional constraints. The synthesized logic resource occupation report is shown in Figure 3.

  

  Figure 3 Logic resource usage after SOC system FPGA synthesis

  According to the timing analysis report, the actual operating frequency of the SoC system can reach 65.31 MHz under the premise of meeting timing.

  
  

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  Hardy Posted on 2020/12/25 23:32:52

  5 SoC system verification platform software support

  Taking into account the hardware components included in the SoC verification platform and the specific applications of the platform, the main composition of the system software is shown in Figure 4. Mini Bootloader is responsible for loading the application program from the Flash device to the program running space. On the DE2-70 development board, with the help of NiosII development tools and the SOPC hardware system based on NiosII that comes with the development board, it is very convenient to program Flash. When the system starts, it can start from Flash, and then jump to the memory space where the main program runs after completing the copy of the application program. In this system, in order to make programming more convenient, the copy program is stored in the on-chip RAM. The system starts from the on-chip RAM, after completing the copy of the application program from Flash to SDRAM, it jumps to SDRAM to start the application program.

  The AEMB microprocessor is 99% compatible with MicroBlaze in terms of instructions, and the latter's application and operating system development already has very mature examples. The migration of the operating system is mainly to complete the modification of the hardware address space and the compilation of some underlying initialization codes of the operating system. Finally, the transplantation of μC/OS-II was completed on the SoC system verification platform.

  Conclusion

  This paper designs a SoC system verification platform based on the 32-bit microprocessor AEMB, and gives the logic resource occupancy of the SoC system after FPGA synthesis and the highest clock frequency that the system can run. The platform has completed FPGA verification on the DE2-70 development board of Taiwan Friends of the Crystal Company.

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