The hardware I use now is cy7c68013A +EP1c6q240+256KB of SRAM; the function that needs to be realized: use FPGA to collect external data (6M, 8bit), store it in SRAM, and use 48M speed to store the data through cy7c68013A (FIFO SLAVE EP6 512X) 2 AUTOIN) to the computer. The question now is: how does FPGA deal with the conflict between 6M write and 48M read (almost simultaneous read and write), please help from experts, thank you.