The younger brother is learning the ip core of ddr2 of quartus ii recently, and wrote a program, instantiated the ip sum of DDR2 in the program, want to use modelsim to see the waveform, only functional simulation (RTL simulation), but there are many simulations The same error is as follows. Have you ever encountered such a situation? How is it solved?

# ** Error: (vsim-3584) C:/Users/Administrator/Desktop/ddr2_ceshi/ddr2_ip_sim/ddr2_ip/alt_mem_ddrx_controller.v(2256): Module parameter'CFG_MEM_IF_CS_WIDTH' not found for override.

#

# Region: /ddr2_ceshi_vlg_tst/i1/if0/ddr2_ip_inst/c0/ng0/alt_mem_ddrx_controller_top_inst/controller_inst

# ** Error: (vsim-3584) C:/Users/Administrator/Desktop/ddr2_ceshi/ddr2_ip_sim/ddr2_ip/alt_mem_ddrx_controller.v(2256): Module parameter'CFG_RANK_tiMER_OUTPUT_REG' not found for override.

#

# Region: /ddr2_ceshi_vlg_tst/i1/if0/ddr2_ip_inst/c0/ng0/alt_mem_ddrx_controller_top_inst/controller_inst

# ** Error: (vsim-3584) C:/Users/Administrator/Desktop/ddr2_ceshi/ddr2_ip_sim/ddr2_ip/alt_mem_ddrx_controller.v(2328): Module parameter'CFG_RANK_TIMER_OUTPUT_REG' not found for override.

#

# Region: /ddr2_ceshi_vlg_tst/i1/if0/ddr2_ip_inst/c0/ng0/alt_mem_ddrx_controller_top_inst/controller_inst

# ** Error: (vsim-3584) C:/Users/Administrator/Desktop/ddr2_ceshi/ddr2_ip_sim/ddr2_ip/alt_mem_ddrx_controller.v(2508): Module parameter'CFG_CTL_ARBITER_TYPE' not found for override.

#

# Region: /ddr2_ceshi_vlg_tst/i1/if0/ddr2_ip_inst/c0/ng0/alt_mem_ddrx_controller_top_inst/controller_inst

# Loading a0.alt_mem_ddrx_mm_st_converter

# Loading oct0.altera_mem_if_oct_cyclonev

# Loading dll0.altera_mem_if_dll_cyclonev

# Error loading design

# Error: Error loading design

# Pausing macro execution

# MACRO ./ddr2_ceshi_run_msim_rtl_verilog.do PAUSED at line 214


I couldn't find this mistake on internet, and I couldn't figure it out. Thank you, brother!

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