As shown in the figure: Input SW value, but it becomes high resistance z during simulation. Do not know where to enter the problem.
Author: Allen Chi Aug 05, 2020 1886
As shown in the figure: Input SW value, but it becomes high resistance z during simulation. Do not know where to enter the problem.
Noah Posted on 2020/8/5 16:04:35
Uncertain state, logic is flawed.
Reply 0
Posted on 2020/8/5 16:05:21
Noah Reply
Excuse me, how do I add it specifically, because I didn't know it clearly just after learning.
Reply 0
Larry Posted on 2020/8/5 16:04:56
Add a reset signal to it.
Reply 0
Posted on 2020/8/5 16:06:03
Larry Reply
I tried to add the base number grid to the SW signal: 00000100 changed to 8'b00000100, and the simulation signal was correct.
Reply 0Manufacturer:Xilinx
Product Categories: CPLD/FPGA
Lifecycle:Obsolete -
RoHS: No RoHS
Manufacturer:Xilinx
Product Categories:
Lifecycle:Obsolete -
RoHS:
Manufacturer:Xilinx
Product Categories: Embedded - FPGAs (Field Programmable Gate Array)
Lifecycle:Active Active
RoHS:
Manufacturer:Xilinx
Product Categories: FPGAs (Field Programmable Gate Array)
Lifecycle:Active Active
RoHS: No RoHS
Manufacturer:Xilinx
Product Categories: FPGAs (Field Programmable Gate Array)
Lifecycle:Active Active
RoHS: No RoHS
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