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Verilog assign keyword, can it be used like this?

Author: sonia touati Aug 05, 2020 1696

assign a=[5:3]SW; //Use SW5~SW3 as an operand.

The original intention is to treat SW2~SW0, SW5~SW3, SW7~SW6 of [7:0]SW as several operands respectively. I want to know if I can write like this if only the middle bits are operated.

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XC4005E-1PC84C

Manufacturer:Xilinx
FPGA XC4000E Family 5K Gates 466 Cells 0.35um Technology 5V 84-Pin PLCC
Product Categories: CPLD/FPGA

Lifecycle:Obsolete -

RoHS: No RoHS

XC4036XL-3HQ208C

Manufacturer:Xilinx
FPGA XC4000X Family 36K Gates 3078 Cells 0.35um Technology 3.3V 208-Pin HSPQFP EP
Product Categories: FPGAs (Field Programmable Gate Array)

Lifecycle:Obsolete -

RoHS: No RoHS

XC5VLX30-1FFG324CES

Manufacturer:Xilinx
FPGA Virtex-5 LX Family 30720 Cells 65nm Technology 1V 324-Pin FCBGA
Product Categories: Connecteurs

Lifecycle:Unconfirmed -

RoHS:

XC5VLX30-2FF324I

Manufacturer:Xilinx
FPGA Virtex-5 LX Family 30720 Cells 65nm Technology 1V 324-Pin FCBGA
Product Categories: FPGAs

Lifecycle:Active Active

RoHS: No RoHS

XC5VLX30-2FFG324I

Manufacturer:Xilinx
FPGA Virtex-5 LX Family 30720 Cells 65nm Technology 1V 324-Pin FCBGA
Product Categories: FPGAs (Field Programmable Gate Array)

Lifecycle:Active Active

RoHS:

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Verilog assign keyword, can it be used like this?

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