Is the highest frequency of the DSP on V6 related to the bit width of the multiplication?

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  Jerome Posted on 2020/7/23 14:47:54

  This should mean that a single DSP48E1 hard DSP can run to 600MHz, which means that the delay of DSP48E1 is 1/600M second

  When using a core generator to generate multipliers with different digits, multiple DSP48E1 units may be needed for splicing. At this time, your multiplier must be less than 600MHz.

  How many DSP48E1s are needed for splicing can be seen from the core generator interface

  For details on how to stitch, please use the FPGA editor to observe.

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    Posted on 2020/7/23 14:48:12

    Jerome Reply

    What if it is within 25 bits by 18 bits? In other words, a single DSP48E1 can handle multiplication.

    For example: 25 bits * 18 bits and 10 bits * 10 bits, can both run to 600MHz?

    
    

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• 

  Gino Posted on 2020/7/23 14:48:51

  Up to 600Mhz in the User Guide. It is the most ideal state for single-core operation.

  In actual applications, it will be restricted by other factors... Besides, it is not ideal for any device to operate in an extreme state.

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• 

  Edgar Posted on 2020/7/23 14:49:45

  Assuming that the other factors are the same, in this case, the achievable frequency of the two multiplications of 25 bits * 18 bits and 10 bits * 10 bits should be about the same?

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    Posted on 2020/7/23 14:49:56

    Edgar Reply

    This is normal, because each DSP48 is a hard core, and 25X18 is dead.

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