Hello everyone, I encountered a problem when using PCI expess IP core to make a device. I came up to ask everyone, how should I solve it?
I used PCI express v1.7 to generate an EP, and then wrote some user logic on the transcation layer. After the device code was burned into the device, it was inserted into the PCI express slot of the motherboard, and then the device driver reads and writes the device in PIO mode. I can read and write accurately, but I found that there is a big problem with the speed. Then I checked the link speed and width of the device and found that the training results are very bad!
The configuration information of the device is:
PCI express GEN I x8, or PCI express GEN II x4
But I use lspci -vvvv, the actual link information obtained is:
PCI express GEN I x1
Such speed and bandwidth greatly reduce the transmission efficiency of the device! So I was considering whether my equipment was not configured properly, and then I found another piece of equipment, PCI express GEN II x8, the result of lspci -vvvv is still PCI express GEN I x1, so I think it should not be the equipment problem. It should be a problem with the motherboard.
Everyone, please help!
