Can you use the Verilog test code, and how to use it if you can, thank you.
Author: Stefan Andrey Jul 23, 2020 2281
Can you use the Verilog test code, and how to use it if you can, thank you.
Mason Posted on 2020/7/23 12:07:44
Modelsim supports hybrid simulation.
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Posted on 2020/7/23 12:09:10
Mason Reply
Enter vsim -t ps in the command line, ps means the simulation accuracy is 1ps.
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Posted on 2020/7/23 12:10:26
Stefan Andrey Reply
Think of the VHDL module as a verilog module. You can write testbench in verilog. In the testbench, you can call the VHDL module according to the method of calling the verilog module.
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Matthew Posted on 2020/7/23 12:08:07
Yes. Just call it directly.
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Posted on 2020/7/23 12:08:32
Matthew Reply
What do you write at the beginning,
For example, when testing verilog, write at the beginning
`timescale 1ns/1ns
`include "./datacheck.v"
How to write if VHDL test.
Reply 0
Joseph Posted on 2020/7/23 12:09:42
Verilog and VHDL are the same.
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