I used syplify2010 to synthesize, always prompt in fit
Cpld:6-Cannot assign GCK Pin i_clk to Pin 50 (FB7_2). This pin does not
support the functionality of that signal.
If it is integrated with XST, there is no problem. Let's see if we can help solve it.
Due to hardware design issues, the i_clk position cannot be changed. The xc95144t100 chip is used.
module d_trig(i_clk, din, dout)
input i_clk,din;
output dout;
reg data;
[email=always@(posedge(clk]always@(posedge(clk[/email]))
begin
data <= din;
end
assign dout = data;
end module;
