Author: Juan Hsiung Jul 07, 2020 1515
BUFGMUX_CTRL is one of two options. I wonder if Xilinx can be designed as one of three in the future product line and increase the clock input? Of course, if you can bring some simple frequency division capabilities like BUFR, it is even better.
When actually used, there are more clock switches, and the number of BUFGs is tight.
Maybe I'm too greedy, I don't know how difficult it is to achieve, but I just "whimsical" myself, hehe.
Kenny Posted on 2020/7/8 13:19:51
In the V5 era, Budg can be connected to PMCD, with simple crossover function and phase alignment function. But it seems that not many people use it.
Is there any need to choose one of the three clocks?
The only application I can think of is tri-mode Ethernet, but this is because subsequent devices basically have a hard core, and generally do not require users to provide a low-speed clock.
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Neil Posted on 2020/7/8 20:07:26
Soft core, listen to others say that this hard core controller is not very good.
Reply 0Manufacturer:Xilinx
Product Categories: Module RF, IC et Accessoires
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Product Categories: FPGAs (Field Programmable Gate Array)
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Manufacturer:Xilinx
Product Categories: FPGAs (Field Programmable Gate Array)
Lifecycle:Obsolete -
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Manufacturer:Xilinx
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