Verilog's two misunderstandings:
Whether to use Reg type or Net type:
The Reg type is only assigned in the process block; the Net type is assigned or driven outside the process block.
Blocking assignment and non-blocking assignment:
Conditions in which competition occurs in Verilog: When two or more statements cause different results when the execution order is different, there is competition.
Nonblocking is not a type;
Blocking assignment is a single-step process, calculating RHS and changing LHS is uninterruptible.
Seven guidelines:
1. Sequential logic and latch, using non-blocking assignment
2. The combinational logic in the always block uses blocking assignment
3. In the same always block, sequential combinational logic uses non-blocking assignment
4. Under normal circumstances, do not mix blocking and non-blocking assignments in the same always block
5. Do not assign the same variable in multiple always blocks
6. Use $strobe to display the non-blocking value-for-money signal
7. Don't use the process of #0 assignment
Layered event queue in Verilog:
Active events: blocking assignment; calculating RHS for non-blocking assignment; continuous assignment; $display command; calculating input and changing the output of the primitive. These events may be scheduled in any order.
Inactive event: #0 blocking assignment
Non-blocking events: update the non-blocking assigned LHS
Monitor event monitor command; $strobe command
experience:
Use non-blocking assignments in the always block to generate sequential logic and latches
Use blocking assignment in the always block to generate combinational logic
Use non-blocking assignment in the always block to generate timing and combinational logic in the same block
Using non-blocking assignments in pure combinatorial logic may result in functional errors
Mixed use of blocking assignment and non-blocking assignment:
The combinational logic assignment is expressed by a sequential expression
Or separate combinatorial logic assignment from sequential logic and describe it in a separate statement block
It is not recommended to mix blocking and non-blocking assignments in the same always block
Several misunderstandings about non-blocking assignment:
Error 1: Unable to display non-blocking assignment variables using the $display command
Positive solution: update of non-blocking assignment variables after all $display commands
Error 2: #0 makes an assignment execute at the end of each time step
Positive solution: #0 will only make the assignment statement enter the inactive event queue
Error 3: Multiple non-blocking assignments to the same variable in the same always block are not allowed
Positive solution: The above assignment is defined in the IEEE 1364 verilog standard, and the last non-blocking assignment works
Difficulties at the beginning of the simulation:
Different simulators, different simulation options lead to different phenomena when starting the simulation
Suggestion: Set reset signal through non-blocking assignment at time 0;
Set clock to 0 in the first half cycle
Some experience in writing Verilog code:
Verilog file name and module name are the same
Don't use casex statements in synthesizable code
Be careful when using casez statements in synthesizable code
When writing case statements, use casez when there are unconcerned cases, use? Instead of Z to indicate unconcerned cases
Verilog writes state machine related:
State machine classification: Moore (output is only related to the current state) and Mealy (output is related to the current state and input)
Binary encoding and One-Hot encoding
The basic blocks of the state machine: combination logic of the next state degree; current state logic of clock synchronization; output combination logic
Two always blocks write state machine, use three always blocks, if the output needs to be registered
Use efficient One-Hot status coding, combined output
experience:
Each state machine acts as an independent Verilog module
Predefine the state, the state assignment uses the state name as a parameter, do not use `define, use parameter more
The state machine of two always statement blocks, one always used to describe the sequential logic of the state vector register. One used to describe the combination logic of the next state degree. The combined output can be described by the continuous assignment statement or in the next state degree combination always block.
