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Home > Forums > Verilog Forum > How to do 2fsk signal generator project?

How to do 2fsk signal generator project?

Author: Sylvia Jul 03, 2020 1782

Recently studying FPGA, the teacher gave a FPGA-based 2fsk signal generator topic, if you have any expert guidance, I am grateful!

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Alfred Posted on 2020/7/4 14:19:36

The landlord estimates that it is not very easy to get started, fsk only needs 1 digital dds, you can change its frequency control word, which is generally found in books.
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Andrew Posted on 2020/7/4 21:07:00

Agree upstairs, mainly dds.
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XC2C512-7FT256C

Manufacturer:Xilinx
CPLD CoolRunner -II Family 12K Gates 512 Macro Cells 179MHz 0.18um Technology 1.8V 256-Pin FTBGA
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XC3SD3400A-4CSG484LI

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FPGA Spartan-3A DSP Family 3.4M Gates 53712 Cells 667MHz 90nm Technology 1.2V 484-Pin BGA
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XC3SD3400A-5CS484C

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FPGA Spartan-3A DSP Family 3.4M Gates 53712 Cells 770MHz 90nm Technology 1.2V 484-Pin LCSBGA
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XC3SD3400A-FGG676I

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Xilinx BGA676
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XC2C512-7PQ208C

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CPLD CoolRunner -II Family 12K Gates 512 Macro Cells 179MHz 0.18um Technology 1.8V 208-Pin PQFP
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